* Globally invalidate the context entries cache, busily waiting for * the completion. */
| 424 | * the completion. |
| 425 | */ |
| 426 | int |
| 427 | dmar_inv_ctx_glob(struct dmar_unit *unit) |
| 428 | { |
| 429 | int error; |
| 430 | |
| 431 | /* |
| 432 | * Access to the CCMD register must be serialized while the |
| 433 | * command is submitted. |
| 434 | */ |
| 435 | DMAR_ASSERT_LOCKED(unit); |
| 436 | KASSERT(!unit->qi_enabled, ("QI enabled")); |
| 437 | |
| 438 | /* |
| 439 | * The DMAR_CCMD_ICC bit in the upper dword should be written |
| 440 | * after the low dword write is completed. Amd64 |
| 441 | * dmar_write8() does not have this issue, i386 dmar_write8() |
| 442 | * writes the upper dword last. |
| 443 | */ |
| 444 | dmar_write8(unit, DMAR_CCMD_REG, DMAR_CCMD_ICC | DMAR_CCMD_CIRG_GLOB); |
| 445 | DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_CCMD_REG + 4) & DMAR_CCMD_ICC32) |
| 446 | == 0)); |
| 447 | return (error); |
| 448 | } |
| 449 | |
| 450 | /* |
| 451 | * Globally invalidate the IOTLB, busily waiting for the completion. |
no test coverage detected