| 278 | } |
| 279 | |
| 280 | void |
| 281 | mips_cpu_init(void) |
| 282 | { |
| 283 | platform_cpu_init(); |
| 284 | mips_get_identity(&cpuinfo); |
| 285 | num_tlbentries = cpuinfo.tlb_nentries; |
| 286 | mips_wr_wired(0); |
| 287 | tlb_invalidate_all(); |
| 288 | mips_wr_wired(VMWIRED_ENTRIES); |
| 289 | mips_config_cache(&cpuinfo); |
| 290 | mips_vector_init(); |
| 291 | |
| 292 | mips_icache_sync_all(); |
| 293 | mips_dcache_wbinv_all(); |
| 294 | } |
| 295 | |
| 296 | void |
| 297 | cpu_identify(void) |
no test coverage detected