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Function mips_vector_init

freebsd/mips/mips/machdep.c:327–378  ·  view source on GitHub ↗

* Initialize the hardware exception vectors, and the jump table used to * call locore cache and TLB management functions, based on the kind * of CPU the kernel is running on. */

Source from the content-addressed store, hash-verified

325 * of CPU the kernel is running on.
326 */
327void
328mips_vector_init(void)
329{
330 /*
331 * Make sure that the Wait region logic is not been
332 * changed
333 */
334 if (MipsWaitEnd - MipsWaitStart != 16)
335 panic("startup: MIPS wait region not correct");
336 /*
337 * Copy down exception vector code.
338 */
339 if (MipsTLBMissEnd - MipsTLBMiss > 0x80)
340 panic("startup: UTLB code too large");
341
342 if (MipsCacheEnd - MipsCache > 0x80)
343 panic("startup: Cache error code too large");
344
345 bcopy(MipsTLBMiss, (void *)MIPS_UTLB_MISS_EXC_VEC,
346 MipsTLBMissEnd - MipsTLBMiss);
347
348 /*
349 * XXXRW: Why don't we install the XTLB handler for all 64-bit
350 * architectures?
351 */
352#if defined(__mips_n64) || defined(CPU_RMI) || defined(CPU_NLM) || defined(CPU_BERI)
353/* Fake, but sufficient, for the 32-bit with 64-bit hardware addresses */
354 bcopy(MipsTLBMiss, (void *)MIPS_XTLB_MISS_EXC_VEC,
355 MipsTLBMissEnd - MipsTLBMiss);
356#endif
357
358 bcopy(MipsException, (void *)MIPS_GEN_EXC_VEC,
359 MipsExceptionEnd - MipsException);
360
361 bcopy(MipsCache, (void *)MIPS_CACHE_ERR_EXC_VEC,
362 MipsCacheEnd - MipsCache);
363
364 /*
365 * Clear out the I and D caches.
366 */
367 mips_icache_sync_all();
368 mips_dcache_wbinv_all();
369
370 /*
371 * Mask all interrupts. Each interrupt will be enabled
372 * when handler is installed for it
373 */
374 set_intr_mask(0);
375
376 /* Clear BEV in SR so we start handling our own exceptions */
377 mips_wr_status(mips_rd_status() & ~MIPS_SR_BEV);
378}
379
380/*
381 * Fix kernel_kseg0_end address in case trampoline placed debug sympols

Callers 1

mips_cpu_initFunction · 0.85

Calls 2

set_intr_maskFunction · 0.85
panicFunction · 0.50

Tested by

no test coverage detected