| 88 | #endif |
| 89 | |
| 90 | void |
| 91 | mips_config_cache(struct mips_cpuinfo * cpuinfo) |
| 92 | { |
| 93 | |
| 94 | switch (cpuinfo->l1.ic_linesize) { |
| 95 | case 16: |
| 96 | mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_16; |
| 97 | mips_cache_ops.mco_icache_sync_range = |
| 98 | mipsNN_icache_sync_range_16; |
| 99 | mips_cache_ops.mco_icache_sync_range_index = |
| 100 | mipsNN_icache_sync_range_index_16; |
| 101 | break; |
| 102 | case 32: |
| 103 | mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_32; |
| 104 | mips_cache_ops.mco_icache_sync_range = |
| 105 | mipsNN_icache_sync_range_32; |
| 106 | mips_cache_ops.mco_icache_sync_range_index = |
| 107 | mipsNN_icache_sync_range_index_32; |
| 108 | break; |
| 109 | case 64: |
| 110 | mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_64; |
| 111 | mips_cache_ops.mco_icache_sync_range = |
| 112 | mipsNN_icache_sync_range_64; |
| 113 | mips_cache_ops.mco_icache_sync_range_index = |
| 114 | mipsNN_icache_sync_range_index_64; |
| 115 | break; |
| 116 | case 128: |
| 117 | mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_128; |
| 118 | mips_cache_ops.mco_icache_sync_range = |
| 119 | mipsNN_icache_sync_range_128; |
| 120 | mips_cache_ops.mco_icache_sync_range_index = |
| 121 | mipsNN_icache_sync_range_index_128; |
| 122 | break; |
| 123 | |
| 124 | #ifdef MIPS_DISABLE_L1_CACHE |
| 125 | case 0: |
| 126 | mips_cache_ops.mco_icache_sync_all = (void (*)(void))cache_noop; |
| 127 | mips_cache_ops.mco_icache_sync_range = cache_noop; |
| 128 | mips_cache_ops.mco_icache_sync_range_index = cache_noop; |
| 129 | break; |
| 130 | #endif |
| 131 | default: |
| 132 | panic("no Icache ops for %d byte lines", |
| 133 | cpuinfo->l1.ic_linesize); |
| 134 | } |
| 135 | |
| 136 | switch (cpuinfo->l1.dc_linesize) { |
| 137 | case 16: |
| 138 | mips_cache_ops.mco_pdcache_wbinv_all = |
| 139 | mips_cache_ops.mco_intern_pdcache_wbinv_all = |
| 140 | mipsNN_pdcache_wbinv_all_16; |
| 141 | mips_cache_ops.mco_pdcache_wbinv_range = |
| 142 | mipsNN_pdcache_wbinv_range_16; |
| 143 | mips_cache_ops.mco_pdcache_wbinv_range_index = |
| 144 | mips_cache_ops.mco_intern_pdcache_wbinv_range_index = |
| 145 | mipsNN_pdcache_wbinv_range_index_16; |
| 146 | mips_cache_ops.mco_pdcache_inv_range = |
| 147 | mipsNN_pdcache_inv_range_16; |
no test coverage detected