* Perform the guaranteed invalidation of all TLB entries. This * includes the global entries, and entries in all PCIDs, not only the * current context. The function works both on non-PCID CPUs and CPUs * with the PCID turned off or on. See IA-32 SDM Vol. 3a 4.10.4.1 * Operations that Invalidate TLBs and Paging-Structure Caches. */
| 501 | * Operations that Invalidate TLBs and Paging-Structure Caches. |
| 502 | */ |
| 503 | static __inline void |
| 504 | invltlb_glob(void) |
| 505 | { |
| 506 | uint64_t cr4; |
| 507 | |
| 508 | cr4 = rcr4(); |
| 509 | load_cr4(cr4 & ~CR4_PGE); |
| 510 | /* |
| 511 | * Although preemption at this point could be detrimental to |
| 512 | * performance, it would not lead to an error. PG_G is simply |
| 513 | * ignored if CR4.PGE is clear. Moreover, in case this block |
| 514 | * is re-entered, the load_cr4() either above or below will |
| 515 | * modify CR4.PGE flushing the TLB. |
| 516 | */ |
| 517 | load_cr4(cr4 | CR4_PGE); |
| 518 | } |
| 519 | |
| 520 | /* |
| 521 | * TLB flush for an individual page (even if it has PG_G). |
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