| 857 | } |
| 858 | |
| 859 | static void |
| 860 | invltlb_pcid_handler(pmap_t smp_tlb_pmap) |
| 861 | { |
| 862 | uint32_t pcid; |
| 863 | |
| 864 | #ifdef COUNT_XINVLTLB_HITS |
| 865 | xhits_gbl[PCPU_GET(cpuid)]++; |
| 866 | #endif /* COUNT_XINVLTLB_HITS */ |
| 867 | #ifdef COUNT_IPIS |
| 868 | (*ipi_invltlb_counts[PCPU_GET(cpuid)])++; |
| 869 | #endif /* COUNT_IPIS */ |
| 870 | |
| 871 | if (smp_tlb_pmap == kernel_pmap) { |
| 872 | invltlb_glob(); |
| 873 | } else { |
| 874 | /* |
| 875 | * The current pmap might not be equal to |
| 876 | * smp_tlb_pmap. The clearing of the pm_gen in |
| 877 | * pmap_invalidate_all() takes care of TLB |
| 878 | * invalidation when switching to the pmap on this |
| 879 | * CPU. |
| 880 | */ |
| 881 | if (smp_tlb_pmap == PCPU_GET(curpmap)) { |
| 882 | pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid; |
| 883 | load_cr3(smp_tlb_pmap->pm_cr3 | pcid); |
| 884 | if (smp_tlb_pmap->pm_ucr3 != PMAP_NO_CR3) |
| 885 | PCPU_SET(ucr3_load_mask, ~CR3_PCID_SAVE); |
| 886 | } |
| 887 | } |
| 888 | } |
| 889 | |
| 890 | static void |
| 891 | invlpg_handler(vm_offset_t smp_tlb_addr1) |
no test coverage detected