* After changing the page size for the specified virtual address in the page * table, flush the corresponding entries from the processor's TLB. Only the * calling processor's TLB is affected. * * The calling thread must be pinned to a processor. */
| 2666 | * The calling thread must be pinned to a processor. |
| 2667 | */ |
| 2668 | static void |
| 2669 | pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde) |
| 2670 | { |
| 2671 | pt_entry_t PG_G; |
| 2672 | |
| 2673 | if (pmap_type_guest(pmap)) |
| 2674 | return; |
| 2675 | |
| 2676 | KASSERT(pmap->pm_type == PT_X86, |
| 2677 | ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type)); |
| 2678 | |
| 2679 | PG_G = pmap_global_bit(pmap); |
| 2680 | |
| 2681 | if ((newpde & PG_PS) == 0) |
| 2682 | /* Demotion: flush a specific 2MB page mapping. */ |
| 2683 | invlpg(va); |
| 2684 | else if ((newpde & PG_G) == 0) |
| 2685 | /* |
| 2686 | * Promotion: flush every 4KB page mapping from the TLB |
| 2687 | * because there are too many to flush individually. |
| 2688 | */ |
| 2689 | invltlb(); |
| 2690 | else { |
| 2691 | /* |
| 2692 | * Promotion: flush every 4KB page mapping from the TLB, |
| 2693 | * including any global (PG_G) mappings. |
| 2694 | */ |
| 2695 | invltlb_glob(); |
| 2696 | } |
| 2697 | } |
| 2698 | |
| 2699 | /* |
| 2700 | * The amd64 pmap uses different approaches to TLB invalidation |
no test coverage detected