* ixgbe_pcie_timeout_poll - Return number of times to poll for completion * @hw: pointer to hardware structure * * System-wide timeout range is encoded in PCIe Device Control2 register. * * Add 10% to specified maximum and return the number of times to poll for * completion timeout, in units of 100 microsec. Never return less than * 800 = 80 millisec. */
| 3131 | * 800 = 80 millisec. |
| 3132 | */ |
| 3133 | STATIC u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) |
| 3134 | { |
| 3135 | s16 devctl2; |
| 3136 | u32 pollcnt; |
| 3137 | |
| 3138 | devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2); |
| 3139 | devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK; |
| 3140 | |
| 3141 | switch (devctl2) { |
| 3142 | case IXGBE_PCIDEVCTRL2_65_130ms: |
| 3143 | pollcnt = 1300; /* 130 millisec */ |
| 3144 | break; |
| 3145 | case IXGBE_PCIDEVCTRL2_260_520ms: |
| 3146 | pollcnt = 5200; /* 520 millisec */ |
| 3147 | break; |
| 3148 | case IXGBE_PCIDEVCTRL2_1_2s: |
| 3149 | pollcnt = 20000; /* 2 sec */ |
| 3150 | break; |
| 3151 | case IXGBE_PCIDEVCTRL2_4_8s: |
| 3152 | pollcnt = 80000; /* 8 sec */ |
| 3153 | break; |
| 3154 | case IXGBE_PCIDEVCTRL2_17_34s: |
| 3155 | pollcnt = 34000; /* 34 sec */ |
| 3156 | break; |
| 3157 | case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */ |
| 3158 | case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */ |
| 3159 | case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */ |
| 3160 | case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */ |
| 3161 | default: |
| 3162 | pollcnt = 800; /* 80 millisec minimum */ |
| 3163 | break; |
| 3164 | } |
| 3165 | |
| 3166 | /* add 10% to spec maximum */ |
| 3167 | return (pollcnt * 11) / 10; |
| 3168 | } |
| 3169 | |
| 3170 | /** |
| 3171 | * ixgbe_disable_pcie_master - Disable PCI-express master access |
no outgoing calls
no test coverage detected