* ixgbe_disable_pcie_master - Disable PCI-express master access * @hw: pointer to hardware structure * * Disables PCI-Express master access and verifies there are no pending * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS * is returned signifying master requests disabled. **/
| 3177 | * is returned signifying master requests disabled. |
| 3178 | **/ |
| 3179 | s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) |
| 3180 | { |
| 3181 | s32 status = IXGBE_SUCCESS; |
| 3182 | u32 i, poll; |
| 3183 | u16 value; |
| 3184 | |
| 3185 | DEBUGFUNC("ixgbe_disable_pcie_master"); |
| 3186 | |
| 3187 | /* Always set this bit to ensure any future transactions are blocked */ |
| 3188 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); |
| 3189 | |
| 3190 | /* Exit if master requests are blocked */ |
| 3191 | if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || |
| 3192 | IXGBE_REMOVED(hw->hw_addr)) |
| 3193 | goto out; |
| 3194 | |
| 3195 | /* Poll for master request bit to clear */ |
| 3196 | for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { |
| 3197 | usec_delay(100); |
| 3198 | if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) |
| 3199 | goto out; |
| 3200 | } |
| 3201 | |
| 3202 | /* |
| 3203 | * Two consecutive resets are required via CTRL.RST per datasheet |
| 3204 | * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine |
| 3205 | * of this need. The first reset prevents new master requests from |
| 3206 | * being issued by our device. We then must wait 1usec or more for any |
| 3207 | * remaining completions from the PCIe bus to trickle in, and then reset |
| 3208 | * again to clear out any effects they may have had on our device. |
| 3209 | */ |
| 3210 | DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n"); |
| 3211 | hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; |
| 3212 | |
| 3213 | if (hw->mac.type >= ixgbe_mac_X550) |
| 3214 | goto out; |
| 3215 | |
| 3216 | /* |
| 3217 | * Before proceeding, make sure that the PCIe block does not have |
| 3218 | * transactions pending. |
| 3219 | */ |
| 3220 | poll = ixgbe_pcie_timeout_poll(hw); |
| 3221 | for (i = 0; i < poll; i++) { |
| 3222 | usec_delay(100); |
| 3223 | value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); |
| 3224 | if (IXGBE_REMOVED(hw->hw_addr)) |
| 3225 | goto out; |
| 3226 | if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) |
| 3227 | goto out; |
| 3228 | } |
| 3229 | |
| 3230 | ERROR_REPORT1(IXGBE_ERROR_POLLING, |
| 3231 | "PCIe transaction pending bit also did not clear.\n"); |
| 3232 | status = IXGBE_ERR_MASTER_REQUESTS_PENDING; |
| 3233 | |
| 3234 | out: |
| 3235 | return status; |
| 3236 | } |
no test coverage detected