| 1694 | } |
| 1695 | |
| 1696 | void ena_com_admin_destroy(struct ena_com_dev *ena_dev) |
| 1697 | { |
| 1698 | struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; |
| 1699 | struct ena_com_admin_cq *cq = &admin_queue->cq; |
| 1700 | struct ena_com_admin_sq *sq = &admin_queue->sq; |
| 1701 | struct ena_com_aenq *aenq = &ena_dev->aenq; |
| 1702 | u16 size; |
| 1703 | |
| 1704 | ena_com_free_ena_admin_queue_comp_ctx(ena_dev, admin_queue); |
| 1705 | |
| 1706 | size = ADMIN_SQ_SIZE(admin_queue->q_depth); |
| 1707 | if (sq->entries) |
| 1708 | ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, sq->entries, |
| 1709 | sq->dma_addr, sq->mem_handle); |
| 1710 | sq->entries = NULL; |
| 1711 | |
| 1712 | size = ADMIN_CQ_SIZE(admin_queue->q_depth); |
| 1713 | if (cq->entries) |
| 1714 | ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, cq->entries, |
| 1715 | cq->dma_addr, cq->mem_handle); |
| 1716 | cq->entries = NULL; |
| 1717 | |
| 1718 | size = ADMIN_AENQ_SIZE(aenq->q_depth); |
| 1719 | if (ena_dev->aenq.entries) |
| 1720 | ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, aenq->entries, |
| 1721 | aenq->dma_addr, aenq->mem_handle); |
| 1722 | aenq->entries = NULL; |
| 1723 | ENA_SPINLOCK_DESTROY(admin_queue->q_lock); |
| 1724 | } |
| 1725 | |
| 1726 | void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling) |
| 1727 | { |
no test coverage detected