| 2023 | } |
| 2024 | |
| 2025 | int ena_com_admin_init(struct ena_com_dev *ena_dev, |
| 2026 | struct ena_aenq_handlers *aenq_handlers) |
| 2027 | { |
| 2028 | struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; |
| 2029 | u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high; |
| 2030 | int ret; |
| 2031 | |
| 2032 | dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); |
| 2033 | |
| 2034 | if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) { |
| 2035 | ena_trc_err(ena_dev, "Reg read timeout occurred\n"); |
| 2036 | return ENA_COM_TIMER_EXPIRED; |
| 2037 | } |
| 2038 | |
| 2039 | if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) { |
| 2040 | ena_trc_err(ena_dev, "Device isn't ready, abort com init\n"); |
| 2041 | return ENA_COM_NO_DEVICE; |
| 2042 | } |
| 2043 | |
| 2044 | admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH; |
| 2045 | |
| 2046 | admin_queue->bus = ena_dev->bus; |
| 2047 | admin_queue->q_dmadev = ena_dev->dmadev; |
| 2048 | admin_queue->polling = false; |
| 2049 | admin_queue->curr_cmd_id = 0; |
| 2050 | |
| 2051 | ATOMIC32_SET(&admin_queue->outstanding_cmds, 0); |
| 2052 | |
| 2053 | ENA_SPINLOCK_INIT(admin_queue->q_lock); |
| 2054 | |
| 2055 | ret = ena_com_init_comp_ctxt(admin_queue); |
| 2056 | if (ret) |
| 2057 | goto error; |
| 2058 | |
| 2059 | ret = ena_com_admin_init_sq(admin_queue); |
| 2060 | if (ret) |
| 2061 | goto error; |
| 2062 | |
| 2063 | ret = ena_com_admin_init_cq(admin_queue); |
| 2064 | if (ret) |
| 2065 | goto error; |
| 2066 | |
| 2067 | admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + |
| 2068 | ENA_REGS_AQ_DB_OFF); |
| 2069 | |
| 2070 | addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr); |
| 2071 | addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr); |
| 2072 | |
| 2073 | ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF); |
| 2074 | ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF); |
| 2075 | |
| 2076 | addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr); |
| 2077 | addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr); |
| 2078 | |
| 2079 | ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF); |
| 2080 | ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF); |
| 2081 | |
| 2082 | aq_caps = 0; |
no test coverage detected