Function eth_ena_dev_init

dpdk/drivers/net/ena/ena_ethdev.c:2168–2359

}

static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
{
	struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
	struct rte_pci_device *pci_dev;
	struct rte_intr_handle *intr_handle;
	struct ena_adapter *adapter = eth_dev->data->dev_private;
	struct ena_com_dev *ena_dev = &adapter->ena_dev;
	struct ena_com_dev_get_features_ctx get_feat_ctx;
	struct ena_llq_configurations llq_config;
	const char *queue_type_str;
	uint32_t max_num_io_queues;
	int rc;
	static int adapters_found;
	bool disable_meta_caching;

	eth_dev->dev_ops = &ena_dev_ops;
	eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
	eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
	eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;

	rc = ena_init_once();
	if (rc != 0)
		return rc;

	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
		return 0;

	eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;

	memset(adapter, 0, sizeof(struct ena_adapter));
	ena_dev = &adapter->ena_dev;

	adapter->edev_data = eth_dev->data;

	pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);

	PMD_INIT_LOG(INFO, "Initializing " PCI_PRI_FMT "\n",
		     pci_dev->addr.domain,
		     pci_dev->addr.bus,
		     pci_dev->addr.devid,
		     pci_dev->addr.function);

	intr_handle = pci_dev->intr_handle;

	adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
	adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;

	if (!adapter->regs) {
		PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)\n",
			     ENA_REGS_BAR);
		return -ENXIO;
	}

	ena_dev->reg_bar = adapter->regs;
	/* Pass device data as a pointer which can be passed to the IO functions
	 * by the ena_com (for example - the memory allocation).
	 */
	ena_dev->dmadev = eth_dev->data;