| 5337 | } |
| 5338 | |
| 5339 | static void |
| 5340 | eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction, |
| 5341 | uint8_t queue, uint8_t msix_vector) |
| 5342 | { |
| 5343 | uint32_t tmp = 0; |
| 5344 | |
| 5345 | if (hw->mac.type == e1000_82575) { |
| 5346 | if (direction == 0) |
| 5347 | tmp = E1000_EICR_RX_QUEUE0 << queue; |
| 5348 | else if (direction == 1) |
| 5349 | tmp = E1000_EICR_TX_QUEUE0 << queue; |
| 5350 | E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp); |
| 5351 | } else if (hw->mac.type == e1000_82576) { |
| 5352 | if ((direction == 0) || (direction == 1)) |
| 5353 | eth_igb_write_ivar(hw, msix_vector, queue & 0x7, |
| 5354 | ((queue & 0x8) << 1) + |
| 5355 | 8 * direction); |
| 5356 | } else if ((hw->mac.type == e1000_82580) || |
| 5357 | (hw->mac.type == e1000_i350) || |
| 5358 | (hw->mac.type == e1000_i354) || |
| 5359 | (hw->mac.type == e1000_i210) || |
| 5360 | (hw->mac.type == e1000_i211)) { |
| 5361 | if ((direction == 0) || (direction == 1)) |
| 5362 | eth_igb_write_ivar(hw, msix_vector, |
| 5363 | queue >> 1, |
| 5364 | ((queue & 0x1) << 4) + |
| 5365 | 8 * direction); |
| 5366 | } |
| 5367 | } |
| 5368 | |
| 5369 | /* Sets up the hardware to generate MSI-X interrupts properly |
| 5370 | * @hw |
no test coverage detected