Sets up the hardware to generate MSI-X interrupts properly * @hw * board private structure */
| 5371 | * board private structure |
| 5372 | */ |
| 5373 | static void |
| 5374 | eth_igb_configure_msix_intr(struct rte_eth_dev *dev) |
| 5375 | { |
| 5376 | int queue_id, nb_efd; |
| 5377 | uint32_t tmpval, regval, intr_mask; |
| 5378 | struct e1000_hw *hw = |
| 5379 | E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); |
| 5380 | uint32_t vec = E1000_MISC_VEC_ID; |
| 5381 | uint32_t base = E1000_MISC_VEC_ID; |
| 5382 | uint32_t misc_shift = 0; |
| 5383 | struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); |
| 5384 | struct rte_intr_handle *intr_handle = pci_dev->intr_handle; |
| 5385 | |
| 5386 | /* won't configure msix register if no mapping is done |
| 5387 | * between intr vector and event fd |
| 5388 | */ |
| 5389 | if (!rte_intr_dp_is_en(intr_handle)) |
| 5390 | return; |
| 5391 | |
| 5392 | if (rte_intr_allow_others(intr_handle)) { |
| 5393 | vec = base = E1000_RX_VEC_START; |
| 5394 | misc_shift = 1; |
| 5395 | } |
| 5396 | |
| 5397 | /* set interrupt vector for other causes */ |
| 5398 | if (hw->mac.type == e1000_82575) { |
| 5399 | tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT); |
| 5400 | /* enable MSI-X PBA support */ |
| 5401 | tmpval |= E1000_CTRL_EXT_PBA_CLR; |
| 5402 | |
| 5403 | /* Auto-Mask interrupts upon ICR read */ |
| 5404 | tmpval |= E1000_CTRL_EXT_EIAME; |
| 5405 | tmpval |= E1000_CTRL_EXT_IRCA; |
| 5406 | |
| 5407 | E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval); |
| 5408 | |
| 5409 | /* enable msix_other interrupt */ |
| 5410 | E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER); |
| 5411 | regval = E1000_READ_REG(hw, E1000_EIAC); |
| 5412 | E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER); |
| 5413 | regval = E1000_READ_REG(hw, E1000_EIAM); |
| 5414 | E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER); |
| 5415 | } else if ((hw->mac.type == e1000_82576) || |
| 5416 | (hw->mac.type == e1000_82580) || |
| 5417 | (hw->mac.type == e1000_i350) || |
| 5418 | (hw->mac.type == e1000_i354) || |
| 5419 | (hw->mac.type == e1000_i210) || |
| 5420 | (hw->mac.type == e1000_i211)) { |
| 5421 | /* turn on MSI-X capability first */ |
| 5422 | E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE | |
| 5423 | E1000_GPIE_PBA | E1000_GPIE_EIAME | |
| 5424 | E1000_GPIE_NSICR); |
| 5425 | nb_efd = rte_intr_nb_efd_get(intr_handle); |
| 5426 | if (nb_efd < 0) |
| 5427 | return; |
| 5428 | |
| 5429 | intr_mask = RTE_LEN2MASK(nb_efd, uint32_t) << misc_shift; |
| 5430 |
no test coverage detected