| 5322 | } |
| 5323 | |
| 5324 | static void |
| 5325 | eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector, |
| 5326 | uint8_t index, uint8_t offset) |
| 5327 | { |
| 5328 | uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); |
| 5329 | |
| 5330 | /* clear bits */ |
| 5331 | val &= ~((uint32_t)0xFF << offset); |
| 5332 | |
| 5333 | /* write vector and valid bit */ |
| 5334 | val |= (msix_vector | E1000_IVAR_VALID) << offset; |
| 5335 | |
| 5336 | E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val); |
| 5337 | } |
| 5338 | |
| 5339 | static void |
| 5340 | eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction, |
no outgoing calls
no test coverage detected