Broadcast single-precision (32-bit) floating-point value a to all elements of dst. https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index

Extract float from __m128 at index */

Extract float from __m128 at index */

Load 128-bits of integer data from memory into dst. mem_addr does not need to be aligned on any particular boundary. https://www.intel.com/content/www

Macro: Set the rounding mode bits of the MXCSR control and status register to the value in unsigned 32-bit integer a. The rounding mode may contain an

Broadcast double-precision (64-bit) floating-point value a to all elements of dst. https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index

Set packed single-precision (32-bit) floating-point elements in dst with the supplied values. https://www.intel.com/content/www/us/en/docs/intrinsics-

Extract uint32 from __m128 at index (for bit-level comparison) */

Safe float/double to int32_t conversion. * Returns INT32_MIN (0x80000000) for NaN, Inf, or out-of-range values, * matching x86 SSE behavior for cvt*

Quiet NaN (qNaN): exponent all 1s, mantissa MSB = 1 * Standard quiet NaN with canonical payload */

Copy single-precision (32-bit) floating-point element a to the lower element of dst, and zero the upper 3 elements. https://www.intel.com/content/www/

Set the MXCSR control and status register with the value in unsigned 32-bit integer a. https://www.intel.com/content/www/us/en/docs/intrinsics-guide/i

Double precision qNaN */

Extract double from __m128d at index */

Assist in expanding the AES cipher key by computing steps towards generating a round key for encryption cipher using data from a and an 8-bit round co

Copy double-precision (64-bit) floating-point element a to the lower element of dst, and zero the upper element. https://www.intel.com/content/www/us/

Set packed double-precision (64-bit) floating-point elements in dst with the supplied values. https://www.intel.com/content/www/us/en/docs/intrinsics-

Round the packed single-precision (32-bit) floating-point elements in a using the rounding parameter, and store the results as packed single-precision

Produce rounding which is the same as SSE instructions with _MM_ROUND_NEAREST rounding mode

Multiply packed single-precision (32-bit) floating-point elements in a and b, and store the results in dst. https://www.intel.com/content/www/us/en/do

Load 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) from memory into dst. mem_addr does not need to be aligned on a

Return vector of type __m128i with all elements set to zero. https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_setzero

In the absence of crypto extensions, implement aesenc using regular NEON intrinsics instead. See: https://www.workofard.com/2017/01/accelerated-aes-fo

Verify all lanes of __m128 have expected bit pattern */

Loads two double-precision from unaligned memory, floating-point values. https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text

Compare packed single-precision (32-bit) floating-point elements in a and b, and store packed minimum values in dst. dst does not follow the IEEE Stan

Move the lower double-precision (64-bit) floating-point element from b to the lower element of dst, and copy the upper element from a to the upper ele

Divide packed single-precision (32-bit) floating-point elements in a by packed elements in b, and store the results in dst. Due to ARMv7-A NEON's lack

Compare packed single-precision (32-bit) floating-point elements in a and b, and store packed maximum values in dst. dst does not follow the IEEE Stan

Load 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) from memory into dst. mem_addr must be aligned on a 16-byte bou

Store 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) from a into memory. mem_addr does not need to be aligned on an

Store 128-bits of integer data from a into memory. mem_addr does not need to be aligned on any particular boundary. https://www.intel.com/content/www/

Extract uint64 from __m128d at index (for bit-level comparison) */

Perform one round of an AES decryption flow on data (state) in a using the round key in RoundKey, and store the result in dst. https://www.intel.com/c

Round the packed double-precision (64-bit) floating-point elements in a using the rounding parameter, and store the results as packed double-precision

Get the unsigned 32-bit value of the MXCSR control and status register. https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=

Move the lower single-precision (32-bit) floating-point element from b to the lower element of dst, and copy the upper 3 packed elements from a to the

Compute the bitwise XOR of 128 bits (representing integer data) in a and b, and store the result in dst. https://www.intel.com/content/www/us/en/docs/

qNaN with custom payload (bits 0-21 of mantissa) */

Add packed single-precision (32-bit) floating-point elements in a and b, and store the results in dst. https://www.intel.com/content/www/us/en/docs/in

Helper to extract payload from float NaN */

Load 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) from memory into dst. mem_addr must be aligned on a 16-byte bou

IEEE-754 special value generators */

Compute the square root of packed single-precision (32-bit) floating-point elements in a, and store the results in dst. Due to ARMv7-A NEON's lack of

Validate __m128i against expected 16-byte array

Cast vector of type __m128 to type __m128i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero laten

Macro: Get the rounding mode bits from the MXCSR control and status register. The rounding mode may contain any of the following flags: _MM_ROUND_NEAR

Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in a, and store the results in dst. The maximum relativ

Set packed 32-bit integers in dst with the supplied values. https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_set_epi3

For odd rounds (uses SubWord only from word[2], no Rcon)

Compare packed single-precision (32-bit) floating-point elements in a and b for less-than, and store the results in dst. https://www.intel.com/content

Convert packed single-precision (32-bit) floating-point elements in a to packed 32-bit integers, and store the results in dst. x86 returns INT32_MIN (

Copy the lower 32-bit integer in a to dst. https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsi128_si32

Load 128-bits of integer data from memory into dst. mem_addr must be aligned on a 16-byte boundary or a general-protection exception may be generated.

Compare packed double-precision (64-bit) floating-point elements in a and b, and store packed minimum values in dst. https://www.intel.com/content/www

Round the lower double-precision (64-bit) floating-point element in b using the rounding parameter, store the result as a double-precision floating-po

Round the lower single-precision (32-bit) floating-point element in b using the rounding parameter, store the result as a single-precision floating-po

Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in a, and store the results in dst. The max

Return vector of type __m128 with all elements set to zero. https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_setzero_

AES-128 encryption using AES-NI intrinsics */

Cast vector of type __m128i to type __m128. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero laten

Compare packed single-precision (32-bit) floating-point elements in a and b for equality, and store the results in dst. https://www.intel.com/content/

Convert packed single-precision (32-bit) floating-point elements in a to packed 32-bit integers with truncation, and store the results in dst. x86 ret

Set packed 64-bit integers in dst with the supplied values. https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_set_epi6

Safe float/double to integer conversion with x86 SSE semantics. * x86 SSE returns the "integer indefinite" value (0x80000000 for int32, * 0x80000000

Divide packed double-precision (64-bit) floating-point elements in a by packed elements in b, and store the results in dst. https://www.intel.com/cont

Round the packed single-precision (32-bit) floating-point elements in a down to an integer value, and store the results as packed single-precision flo

Set packed 8-bit integers in dst with the supplied values. https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_set_epi8

Perform the InvMixColumns transformation on a and store the result in dst. https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#te

Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in a and then AND with b, and store the results in dst. https://ww

Round the packed single-precision (32-bit) floating-point elements in a up to an integer value, and store the results as packed single-precision float

Perform a carry-less multiplication of two 64-bit integers, selected from a and b according to imm8, and store the results in dst. https://www.intel.c

Compare packed single-precision (32-bit) floating-point elements in a and b to see if either is NaN, and store the results in dst. https://www.intel.c

Compare packed double-precision (64-bit) floating-point elements in a and b, and store packed maximum values in dst. https://www.intel.com/content/www

Fetch the line of data from memory that contains address p to a location in the cache hierarchy specified by the locality hint i. https://www.intel.co

Broadcast 16-bit integer a to all elements of dst. https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_set1_epi16

Broadcast 32-bit integer a to all elements of dst. https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_set1_epi32

Compute the square root of packed double-precision (64-bit) floating-point elements in a, and store the results in dst. https://www.intel.com/content/

Store 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) from a into memory. mem_addr does not need to be aligned on an

Extract values from fuzz input with bounds checking */