| 12355 | } |
| 12356 | |
| 12357 | void wait_cpu_cycle_write(uaecptr addr, int mode, uae_u32 v) |
| 12358 | { |
| 12359 | int ipl = regs.ipl[0]; |
| 12360 | evt_t now = get_cycles(); |
| 12361 | |
| 12362 | sync_cycles(); |
| 12363 | |
| 12364 | x_do_cycles_pre(CYCLE_UNIT); |
| 12365 | |
| 12366 | blt_info.nasty_cnt = blt_info.blit_interrupt_trigger && aga_mode ? -0x7fffffff : 0; |
| 12367 | dma_cycle(&ipl); |
| 12368 | |
| 12369 | #ifdef DEBUGGER |
| 12370 | if (debug_dma) { |
| 12371 | int reg = 0x1100; |
| 12372 | if (mode == -3) { |
| 12373 | reg |= 2; |
| 12374 | } else if (mode < 0) { |
| 12375 | reg |= 4; |
| 12376 | } else if (mode > 0) { |
| 12377 | reg |= 2; |
| 12378 | } else { |
| 12379 | reg |= 1; |
| 12380 | } |
| 12381 | record_dma_write(reg, v, addr, DMARECORD_CPU, 1); |
| 12382 | } |
| 12383 | peekdma_data.mask = 0; |
| 12384 | #endif |
| 12385 | |
| 12386 | if (mode > -2) { |
| 12387 | if (mode < 0) { |
| 12388 | put_long(addr, v); |
| 12389 | } else if (mode > 0) { |
| 12390 | put_word(addr, v); |
| 12391 | } else if (mode == 0) { |
| 12392 | put_byte(addr, v); |
| 12393 | } |
| 12394 | } |
| 12395 | |
| 12396 | x_do_cycles_post(CYCLE_UNIT, v); |
| 12397 | |
| 12398 | regs.chipset_latch_rw = regs.chipset_latch_write = v; |
| 12399 | |
| 12400 | // if IPL fetch was pending and CPU had wait states: |
| 12401 | // Use ipl_pin value from previous cycle |
| 12402 | if (now == regs.ipl_evt) { |
| 12403 | regs.ipl[0] = ipl; |
| 12404 | } |
| 12405 | } |
| 12406 | |
| 12407 | |
| 12408 | uae_u32 wait_cpu_cycle_read_ce020(uaecptr addr, int mode) |
no test coverage detected