| 78 | } |
| 79 | |
| 80 | CpuModel midr_to_model(uint32_t midr) |
| 81 | { |
| 82 | CpuModel model = CpuModel::GENERIC; |
| 83 | |
| 84 | // Unpack variant and CPU ID |
| 85 | const int implementer = (midr >> 24) & 0xFF; |
| 86 | const int variant = (midr >> 20) & 0xF; |
| 87 | const int cpunum = (midr >> 4) & 0xFFF; |
| 88 | |
| 89 | // Only CPUs we have code paths for are detected. All other CPUs can be safely classed as "GENERIC" |
| 90 | if (implementer == 0x41) // Arm CPUs |
| 91 | { |
| 92 | switch (cpunum) |
| 93 | { |
| 94 | case 0xd03: // A53 |
| 95 | case 0xd04: // A35 |
| 96 | model = CpuModel::A53; |
| 97 | break; |
| 98 | case 0xd05: // A55 |
| 99 | if (variant != 0) |
| 100 | { |
| 101 | model = CpuModel::A55r1; |
| 102 | } |
| 103 | else |
| 104 | { |
| 105 | model = CpuModel::A55r0; |
| 106 | } |
| 107 | break; |
| 108 | case 0xd09: // A73 |
| 109 | model = CpuModel::A73; |
| 110 | break; |
| 111 | case 0xd0a: // A75 |
| 112 | if (variant != 0) |
| 113 | { |
| 114 | model = CpuModel::GENERIC_FP16_DOT; |
| 115 | } |
| 116 | else |
| 117 | { |
| 118 | model = CpuModel::GENERIC_FP16; |
| 119 | } |
| 120 | break; |
| 121 | case 0xd0c: // N1 |
| 122 | model = CpuModel::N1; |
| 123 | break; |
| 124 | case 0xd06: // A65 |
| 125 | case 0xd0b: // A76 |
| 126 | case 0xd0d: // A77 |
| 127 | case 0xd0e: // A76AE |
| 128 | case 0xd41: // A78 |
| 129 | case 0xd42: // A78AE |
| 130 | case 0xd4a: // E1 |
| 131 | model = CpuModel::GENERIC_FP16_DOT; |
| 132 | break; |
| 133 | case 0xd40: // V1 |
| 134 | model = CpuModel::V1; |
| 135 | break; |
| 136 | case 0xd44: // X1 |
| 137 | model = CpuModel::X1; |
no outgoing calls
no test coverage detected