| 160 | } // namespace |
| 161 | |
| 162 | CpuIsaInfo init_cpu_isa_from_hwcaps(uint64_t hwcaps, uint64_t hwcaps2, uint32_t midr) |
| 163 | { |
| 164 | CpuIsaInfo isa; |
| 165 | |
| 166 | decode_hwcaps(isa, hwcaps, hwcaps2); |
| 167 | |
| 168 | const CpuModel model = midr_to_model(midr); |
| 169 | allowlisted_model_features(isa, model); |
| 170 | |
| 171 | return isa; |
| 172 | } |
| 173 | |
| 174 | CpuIsaInfo init_cpu_isa_from_regs( |
| 175 | uint64_t isar0, uint64_t isar1, uint64_t pfr0, uint64_t pfr1, uint64_t svefr0, uint64_t smefr0, uint64_t midr) |
no test coverage detected