| 172 | } |
| 173 | |
| 174 | CpuIsaInfo init_cpu_isa_from_regs( |
| 175 | uint64_t isar0, uint64_t isar1, uint64_t pfr0, uint64_t pfr1, uint64_t svefr0, uint64_t smefr0, uint64_t midr) |
| 176 | { |
| 177 | CpuIsaInfo isa; |
| 178 | |
| 179 | decode_regs(isa, isar0, isar1, pfr0, pfr1, svefr0, smefr0); |
| 180 | |
| 181 | const CpuModel model = midr_to_model(midr); |
| 182 | allowlisted_model_features(isa, model); |
| 183 | |
| 184 | return isa; |
| 185 | } |
| 186 | } // namespace cpuinfo |
| 187 | } // namespace arm_compute |
no test coverage detected