| 105 | #endif /* defined(__aarch64__) */ |
| 106 | |
| 107 | void decode_regs(CpuIsaInfo &isa, |
| 108 | const uint64_t isar0, |
| 109 | const uint64_t isar1, |
| 110 | const uint64_t pfr0, |
| 111 | const uint64_t pfr1, |
| 112 | const uint64_t svefr0, |
| 113 | const uint64_t smefr0) |
| 114 | { |
| 115 | auto is_supported = [](uint64_t feature_reg, uint8_t feature_pos) -> bool |
| 116 | { return ((feature_reg >> feature_pos) & 0xf); }; |
| 117 | |
| 118 | // High-level SIMD support |
| 119 | isa.neon = (((pfr0 >> 20) & 0xf) <= 1); |
| 120 | isa.sve = is_supported(pfr0, 32); |
| 121 | isa.fhm = is_supported(isar0, 48); |
| 122 | isa.sve2 = is_supported(svefr0, 0); |
| 123 | isa.sme = is_supported(pfr1, 24); |
| 124 | isa.sme2 = (((pfr1 >> 24) & 0xf) > 1); |
| 125 | |
| 126 | // Data-type support |
| 127 | isa.fp16 = is_supported(pfr0, 16); |
| 128 | isa.bf16 = is_supported(isar1, 44); |
| 129 | isa.svebf16 = is_supported(svefr0, 20); |
| 130 | |
| 131 | // Instruction extensions |
| 132 | isa.dot = is_supported(isar0, 44); |
| 133 | isa.i8mm = is_supported(isar1, 48); |
| 134 | isa.svei8mm = is_supported(svefr0, 44); |
| 135 | isa.svef32mm = is_supported(svefr0, 52); |
| 136 | |
| 137 | // SME features |
| 138 | isa.sme_b16f32 = (smefr0 & (1ULL << 34)); |
| 139 | isa.sme_f16f32 = (smefr0 & (1ULL << 35)); |
| 140 | isa.sme_f32f32 = (smefr0 & (1ULL << 32)); |
| 141 | isa.sme_i8i32 = (((smefr0 >> 36) & 0xF) == 0xF); |
| 142 | } |
| 143 | |
| 144 | /** Handle features from allow-listed models in case of problematic kernels |
| 145 | * |
no test coverage detected