Describes a simple boolean function. Each N-th [`BfOp`] in the program computes the value of output bit 'N'.

Implemented on some type representing an event for a particular platform.

Demonstrate the effects of aliasing BTB entries. Context ======= A "branch target buffer" (BTB) is a structure that maintains information about prev

Operations used to create BTB collisions

Demonstrate the Collide+Probe side-channel. Context ======= The paper[^1] describes a timing side-channel that follows from the implementation of th

[Naively?] try to interfere with two correlated conditional branches. Context ======= Predicting the *direction* of a branch usually entails the fol

Alternate version of [`CorrelatedBranches`], but with a single padding branch taken in a loop some variable number of times. In this case, the correl

Implemented on suitable "input" variable types associated with a particular set of measurements (ie. in [`EventResults`]). NOTE: So far, we really on

Use PMC events to characterize instruction dispatch. Context ======= According to different revisions of the SOG, there are three ways that an x86 i

Explore the data-dependent behavior of the x86 DIV instruction. Scan over the space of input values to DIV and record the latency.

A "dynamic" list of emitter cases (extensible during runtime).

Utility functions you might want on something implementing [DynasmApi].

Demonstrate the behavior of CVE-2022-4543 ("EntryBleed"). Context ======= In Linux, kernel virtual addresses are usually randomized in an attempt t

Set of results associated with a particular experiment.

Simple synthetic example of cache timing with FLUSH+RELOAD. Context ======= This is an example of how speculative loads can leave measurable side-ef

Auto-implemented on function types that are suitable for generating input to a measured function. [PerfectHarness::measure_vary] expects a type like

Create integer physical register file (PRF) pressure. Context ======= Each time we execute an instruction with some register result (apart from ones

Use performance counters to demonstrate some interesting behavior of the `PREFETCH` instruction. Context ======= It is widely known[^1][^2] that imp

Try to intentionally create L1D cache way mispredictions. Context ======= In the Zen 2 microarchitecture, the L1 data cache is 32KiB set-associative

Create load queue pressure. Context ======= In the Zen microarchitecture, a load queue (LDQ) keeps track of pending loads. The capacity of the load