| 231 | } |
| 232 | |
| 233 | static Result ndspInitialize(bool resume) |
| 234 | { |
| 235 | Result rc; |
| 236 | |
| 237 | rc = svcCreateEvent(&irqEvent, RESET_STICKY); |
| 238 | if (R_FAILED(rc)) goto _fail1; |
| 239 | |
| 240 | rc = DSP_RegisterInterruptEvents(irqEvent, DSP_INTERRUPT_PIPE, 2); |
| 241 | if (R_FAILED(rc)) goto _fail2; |
| 242 | |
| 243 | rc = DSP_GetSemaphoreHandle(&dspSem); |
| 244 | if (R_FAILED(rc)) goto _fail3; |
| 245 | |
| 246 | DSP_SetSemaphoreMask(0x2000); |
| 247 | |
| 248 | if (resume) |
| 249 | { |
| 250 | memcpy(ndspVars[5][0], dspVar5Backup, sizeof(dspVar5Backup)); |
| 251 | __dsb(); |
| 252 | } |
| 253 | |
| 254 | u16 val = resume ? 2 : 0; |
| 255 | DSP_WriteProcessPipe(2, &val, 4); |
| 256 | |
| 257 | DSP_SetSemaphore(0x4000); |
| 258 | ndspWaitForIrq(U64_MAX); |
| 259 | |
| 260 | DSP_ReadPipeIfPossible(2, 0, &val, sizeof(val), NULL); |
| 261 | |
| 262 | u16 vars[16]; |
| 263 | DSP_ReadPipeIfPossible(2, 0, vars, val*2, NULL); |
| 264 | for (unsigned i = 0; i < val; i ++) |
| 265 | { |
| 266 | DSP_ConvertProcessAddressFromDspDram(vars[i], (u32*)&ndspVars[i][0]); |
| 267 | DSP_ConvertProcessAddressFromDspDram(vars[i] | 0x10000, (u32*)&ndspVars[i][1]); |
| 268 | } |
| 269 | |
| 270 | DSP_SetSemaphore(0x4000); |
| 271 | frameCount = 0; |
| 272 | ndspFrameId = 4; |
| 273 | ndspSetCounter(0, 4); |
| 274 | ndspFrameId++; |
| 275 | svcSignalEvent(dspSem); |
| 276 | |
| 277 | ndspBufferCurId = ndspFrameId & 1; |
| 278 | ndspBufferId = ndspFrameId & 1; |
| 279 | bDspReady = true; |
| 280 | |
| 281 | if (resume) |
| 282 | { |
| 283 | ndspiDirtyChn(); |
| 284 | ndspiUpdateChn(); |
| 285 | |
| 286 | ndspDirtyMaster(); |
| 287 | ndspUpdateMaster(); |
| 288 | |
| 289 | // TODO: force update effect params |
| 290 | } |
no test coverage detected