Function DecodeVCVTQ

arch/ARM/ARMDisassembler.c:5537–5606

}

static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn,
		uint64_t Address, const void *Decoder)
{
	DecodeStatus S = MCDisassembler_Success;
	bool hasFullFP16 = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFullFP16);
	unsigned Vm, imm, cmode, op;
	unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0);

	Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4);
	Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0);
	Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4);
	imm = fieldFromInstruction_4(Insn, 16, 6);
	cmode = fieldFromInstruction_4(Insn, 8, 4);
	op = fieldFromInstruction_4(Insn, 5, 1);

	// VMOVv4f32 is ambiguous with these decodings.
	if (!(imm & 0x38) && cmode == 0xF) {
		if (op == 1) return MCDisassembler_Fail;
		MCInst_setOpcode(Inst, ARM_VMOVv4f32);
		return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
	}

	// If the top 3 bits of imm are clear, this is a VMOV (immediate)
	if (!(imm & 0x38)) {
		if (cmode == 0xF) {
			if (op == 1) return MCDisassembler_Fail;
			MCInst_setOpcode(Inst, ARM_VMOVv4f32);
		}

		if (hasFullFP16) {
			if (cmode == 0xE) {
				if (op == 1) {
					MCInst_setOpcode(Inst, ARM_VMOVv2i64);
				} else {
					MCInst_setOpcode(Inst, ARM_VMOVv16i8);
				}
			}

			if (cmode == 0xD) {
				if (op == 1) {
					MCInst_setOpcode(Inst, ARM_VMVNv4i32);
				} else {
					MCInst_setOpcode(Inst, ARM_VMOVv4i32);
				}
			}

			if (cmode == 0xC) {
				if (op == 1) {
					MCInst_setOpcode(Inst, ARM_VMVNv4i32);
				} else {
					MCInst_setOpcode(Inst, ARM_VMOVv4i32);
				}
			}
		}

		return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
	}