| 296 | volatile u32 __OSLastInterruptSrr0; |
| 297 | |
| 298 | void __OSDispatchInterrupt(__OSException exception, OSContext* context) |
| 299 | { |
| 300 | u32 intsr; |
| 301 | u32 reg; |
| 302 | OSInterruptMask cause; |
| 303 | OSInterruptMask unmasked; |
| 304 | OSInterruptMask* prio; |
| 305 | __OSInterrupt interrupt; |
| 306 | __OSInterruptHandler handler; |
| 307 | intsr = __PIRegs[0]; |
| 308 | intsr &= ~0x00010000; |
| 309 | |
| 310 | if (intsr == 0 || (intsr & __PIRegs[1]) == 0) |
| 311 | { |
| 312 | OSLoadContext(context); |
| 313 | } |
| 314 | |
| 315 | cause = 0; |
| 316 | |
| 317 | if (intsr & 0x00000080) |
| 318 | { |
| 319 | reg = __MEMRegs[15]; |
| 320 | if (reg & 0x1) |
| 321 | cause |= OS_INTERRUPTMASK_MEM_0; |
| 322 | if (reg & 0x2) |
| 323 | cause |= OS_INTERRUPTMASK_MEM_1; |
| 324 | if (reg & 0x4) |
| 325 | cause |= OS_INTERRUPTMASK_MEM_2; |
| 326 | if (reg & 0x8) |
| 327 | cause |= OS_INTERRUPTMASK_MEM_3; |
| 328 | if (reg & 0x10) |
| 329 | cause |= OS_INTERRUPTMASK_MEM_ADDRESS; |
| 330 | } |
| 331 | |
| 332 | if (intsr & 0x00000040) |
| 333 | { |
| 334 | reg = __DSPRegs[5]; |
| 335 | if (reg & 0x8) |
| 336 | cause |= OS_INTERRUPTMASK_DSP_AI; |
| 337 | if (reg & 0x20) |
| 338 | cause |= OS_INTERRUPTMASK_DSP_ARAM; |
| 339 | if (reg & 0x80) |
| 340 | cause |= OS_INTERRUPTMASK_DSP_DSP; |
| 341 | } |
| 342 | |
| 343 | if (intsr & 0x00000020) |
| 344 | { |
| 345 | reg = __AIRegs[0]; |
| 346 | if (reg & 0x8) |
| 347 | cause |= OS_INTERRUPTMASK_AI_AI; |
| 348 | } |
| 349 | |
| 350 | if (intsr & 0x00000010) |
| 351 | { |
| 352 | reg = __EXIRegs[0]; |
| 353 | if (reg & 0x2) |
| 354 | cause |= OS_INTERRUPTMASK_EXI_0_EXI; |
| 355 | if (reg & 0x8) |
nothing calls this directly
no test coverage detected