NONMATCHING DEBUG
| 116 | |
| 117 | // NONMATCHING DEBUG |
| 118 | void GXSetCPUFifo(GXFifoObj* fifo) |
| 119 | { |
| 120 | __GXFifoObj* realFifo = (__GXFifoObj*)fifo; |
| 121 | BOOL enabled = OSDisableInterrupts(); |
| 122 | |
| 123 | CPUFifo = realFifo; |
| 124 | if (CPUFifo == GPFifo) |
| 125 | { |
| 126 | u32 reg = 0; |
| 127 | |
| 128 | GX_SET_PI_REG(3, (u32)realFifo->base & 0x3FFFFFFF); |
| 129 | GX_SET_PI_REG(4, (u32)realFifo->top & 0x3FFFFFFF); |
| 130 | |
| 131 | SET_REG_FIELD(LINE(691, 691, 695), reg, 21, 5, (u32)realFifo->wrPtr >> 5); |
| 132 | SET_REG_FIELD(LINE(691, 691, 695), reg, 1, 26, 0); |
| 133 | GX_SET_PI_REG(5, reg); |
| 134 | |
| 135 | CPGPLinked = GX_TRUE; |
| 136 | |
| 137 | __GXWriteFifoIntReset(1, 1); |
| 138 | __GXWriteFifoIntEnable(1, 0); |
| 139 | __GXFifoLink(1); |
| 140 | } |
| 141 | else |
| 142 | { |
| 143 | u32 reg; |
| 144 | |
| 145 | if (CPGPLinked) |
| 146 | { |
| 147 | __GXFifoLink(0); |
| 148 | CPGPLinked = GX_FALSE; |
| 149 | } |
| 150 | |
| 151 | __GXWriteFifoIntEnable(0, 0); |
| 152 | reg = 0; |
| 153 | GX_SET_PI_REG(3, (u32)realFifo->base & 0x3FFFFFFF); |
| 154 | GX_SET_PI_REG(4, (u32)realFifo->top & 0x3FFFFFFF); |
| 155 | SET_REG_FIELD(LINE(726, 726, 730), reg, 21, 5, (u32)realFifo->wrPtr >> 5); |
| 156 | SET_REG_FIELD(LINE(726, 726, 730), reg, 1, 26, 0); |
| 157 | GX_SET_PI_REG(5, reg); |
| 158 | } |
| 159 | |
| 160 | PPCSync(); |
| 161 | OSRestoreInterrupts(enabled); |
| 162 | } |
| 163 | |
| 164 | void GXSetGPFifo(GXFifoObj* fifo) |
| 165 | { |
no test coverage detected