| 216 | } |
| 217 | |
| 218 | void __DSP_exec_task(DSPTaskInfo* curr, DSPTaskInfo* next) |
| 219 | { |
| 220 | if (curr) |
| 221 | { |
| 222 | DSPSendMailToDSP((u32)(curr->dram_mmem_addr)); |
| 223 | while (DSPCheckMailToDSP()) |
| 224 | ; |
| 225 | DSPSendMailToDSP((u32)(curr->dram_length)); |
| 226 | while (DSPCheckMailToDSP()) |
| 227 | ; |
| 228 | DSPSendMailToDSP((u32)(curr->dram_addr)); |
| 229 | while (DSPCheckMailToDSP()) |
| 230 | ; |
| 231 | } |
| 232 | else |
| 233 | { |
| 234 | DSPSendMailToDSP((u32)(0)); |
| 235 | while (DSPCheckMailToDSP()) |
| 236 | ; |
| 237 | DSPSendMailToDSP((u32)(0)); |
| 238 | while (DSPCheckMailToDSP()) |
| 239 | ; |
| 240 | DSPSendMailToDSP((u32)(0)); |
| 241 | while (DSPCheckMailToDSP()) |
| 242 | ; |
| 243 | } |
| 244 | |
| 245 | DSPSendMailToDSP((u32)(next->iram_mmem_addr)); |
| 246 | while (DSPCheckMailToDSP()) |
| 247 | ; |
| 248 | DSPSendMailToDSP((u32)(next->iram_length)); |
| 249 | while (DSPCheckMailToDSP()) |
| 250 | ; |
| 251 | DSPSendMailToDSP((u32)(next->iram_addr)); |
| 252 | while (DSPCheckMailToDSP()) |
| 253 | ; |
| 254 | |
| 255 | if (DSP_TASK_STATE_INIT == next->state) |
| 256 | { |
| 257 | DSPSendMailToDSP((u32)(next->dsp_init_vector)); |
| 258 | while (DSPCheckMailToDSP()) |
| 259 | ; |
| 260 | DSPSendMailToDSP((u32)(0)); |
| 261 | while (DSPCheckMailToDSP()) |
| 262 | ; |
| 263 | DSPSendMailToDSP((u32)(0)); |
| 264 | while (DSPCheckMailToDSP()) |
| 265 | ; |
| 266 | DSPSendMailToDSP((u32)(0)); |
| 267 | while (DSPCheckMailToDSP()) |
| 268 | ; |
| 269 | } |
| 270 | else |
| 271 | { |
| 272 | DSPSendMailToDSP((u32)(next->dsp_resume_vector)); |
| 273 | while (DSPCheckMailToDSP()) |
| 274 | ; |
| 275 | DSPSendMailToDSP((u32)(next->dram_mmem_addr)); |
no test coverage detected