| 288 | |
| 289 | #define MSG_BASE 0x80F30000 |
| 290 | void __DSP_boot_task(DSPTaskInfo* task) |
| 291 | { |
| 292 | volatile u32 mail; |
| 293 | |
| 294 | while (!DSPCheckMailFromDSP()) |
| 295 | ; |
| 296 | |
| 297 | mail = DSPReadMailFromDSP(); |
| 298 | |
| 299 | DSPSendMailToDSP(MSG_BASE | 0xA001); |
| 300 | while (DSPCheckMailToDSP()) |
| 301 | { |
| 302 | } |
| 303 | DSPSendMailToDSP((u32)(task->iram_mmem_addr)); |
| 304 | while (DSPCheckMailToDSP()) |
| 305 | { |
| 306 | } |
| 307 | |
| 308 | DSPSendMailToDSP(MSG_BASE | 0xC002); |
| 309 | while (DSPCheckMailToDSP()) |
| 310 | { |
| 311 | } |
| 312 | DSPSendMailToDSP((u32)(task->iram_addr & 0xffff)); |
| 313 | while (DSPCheckMailToDSP()) |
| 314 | { |
| 315 | } |
| 316 | |
| 317 | DSPSendMailToDSP(MSG_BASE | 0xA002); |
| 318 | while (DSPCheckMailToDSP()) |
| 319 | { |
| 320 | } |
| 321 | DSPSendMailToDSP(task->iram_length); |
| 322 | while (DSPCheckMailToDSP()) |
| 323 | { |
| 324 | } |
| 325 | |
| 326 | DSPSendMailToDSP(MSG_BASE | 0xB002); |
| 327 | while (DSPCheckMailToDSP()) |
| 328 | { |
| 329 | } |
| 330 | DSPSendMailToDSP(0x00000000); |
| 331 | while (DSPCheckMailToDSP()) |
| 332 | { |
| 333 | } |
| 334 | |
| 335 | DSPSendMailToDSP(MSG_BASE | 0xD001); |
| 336 | while (DSPCheckMailToDSP()) |
| 337 | { |
| 338 | } |
| 339 | DSPSendMailToDSP((u32)(0xffff & task->dsp_init_vector)); |
| 340 | while (DSPCheckMailToDSP()) |
| 341 | { |
| 342 | } |
| 343 | |
| 344 | __DSP_debug_printf("DSP is booting task: 0x%08X\n", task); |
| 345 | __DSP_debug_printf("__DSP_boot_task() : IRAM MMEM ADDR: 0x%08X\n", |
| 346 | (u32)(task->iram_mmem_addr)); |
| 347 | __DSP_debug_printf("__DSP_boot_task() : IRAM DSP ADDR : 0x%08X\n", (u32)(task->iram_addr)); |
no test coverage detected