| 517 | } |
| 518 | |
| 519 | bool X64Instr::GetIndexRegisterAndOffset(int* outRegister, int* outOffset) |
| 520 | { |
| 521 | const MCInstrDesc &instDesc = mX64->mInstrInfo->get(mMCInst.getOpcode()); |
| 522 | |
| 523 | auto form = (instDesc.TSFlags & llvm::X86II::FormMask); |
| 524 | if ((form == llvm::X86II::MRMDestMem) || (form == llvm::X86II::MRMSrcMem) || |
| 525 | ((form >= llvm::X86II::MRM0m) && (form <= llvm::X86II::MRM7m))) |
| 526 | { |
| 527 | int regOffset = 0; |
| 528 | if (form == llvm::X86II::MRMSrcMem) |
| 529 | regOffset = 1; |
| 530 | |
| 531 | auto baseReg = mMCInst.getOperand(regOffset + llvm::X86::AddrBaseReg); |
| 532 | auto scaleAmt = mMCInst.getOperand(regOffset + llvm::X86::AddrScaleAmt); |
| 533 | auto indexReg = mMCInst.getOperand(regOffset + llvm::X86::AddrIndexReg); |
| 534 | auto addrDisp = mMCInst.getOperand(regOffset + llvm::X86::AddrDisp); |
| 535 | |
| 536 | /*bool a = baseReg.isReg(); |
| 537 | bool b = scaleAmt.isImm(); |
| 538 | int c = scaleAmt.getImm(); |
| 539 | bool d = indexReg.isReg(); |
| 540 | int e = indexReg.getReg(); |
| 541 | bool f = addrDisp.isImm();*/ |
| 542 | |
| 543 | bool isValid = false; |
| 544 | |
| 545 | // Look for [reg+offset] form |
| 546 | if ((baseReg.isReg()) && |
| 547 | (scaleAmt.isImm()) && (scaleAmt.getImm() == 1) && |
| 548 | (indexReg.isReg()) && (indexReg.getReg() == llvm::X86::NoRegister) && |
| 549 | (addrDisp.isImm())) |
| 550 | { |
| 551 | int regNum = ConvertRegNum(baseReg); |
| 552 | if (regNum == -1) |
| 553 | return false; |
| 554 | *outRegister = regNum; |
| 555 | *outOffset = (int)addrDisp.getImm(); |
| 556 | return true; |
| 557 | } |
| 558 | } |
| 559 | return false; |
| 560 | } |
| 561 | |
| 562 | bool X64Instr::GetImmediate(uint64* outImm) |
| 563 | { |
nothing calls this directly
no test coverage detected