| 375 | } |
| 376 | |
| 377 | static int ConvertRegNum(const MCOperand& operand) |
| 378 | { |
| 379 | if (!operand.isReg()) |
| 380 | return -1; |
| 381 | |
| 382 | switch (operand.getReg()) |
| 383 | { |
| 384 | case llvm::X86::AL: |
| 385 | case llvm::X86::AH: |
| 386 | case llvm::X86::EAX: |
| 387 | case llvm::X86::RAX: |
| 388 | return X64Reg_RAX; |
| 389 | case llvm::X86::CL: |
| 390 | case llvm::X86::CH: |
| 391 | case llvm::X86::ECX: |
| 392 | case llvm::X86::RCX: |
| 393 | return X64Reg_RCX; |
| 394 | case llvm::X86::DL: |
| 395 | case llvm::X86::DH: |
| 396 | case llvm::X86::EDX: |
| 397 | case llvm::X86::RDX: |
| 398 | return X64Reg_RDX; |
| 399 | case llvm::X86::BL: |
| 400 | case llvm::X86::BH: |
| 401 | case llvm::X86::EBX: |
| 402 | case llvm::X86::RBX: |
| 403 | return X64Reg_RBX; |
| 404 | case llvm::X86::RBP: |
| 405 | return X64Reg_RBP; |
| 406 | case llvm::X86::RSP: |
| 407 | return X64Reg_RSP; |
| 408 | |
| 409 | case llvm::X86::R8: |
| 410 | case llvm::X86::R8D: |
| 411 | case llvm::X86::R8W: |
| 412 | case llvm::X86::R8B: |
| 413 | return X64Reg_R8; |
| 414 | case llvm::X86::R9: |
| 415 | case llvm::X86::R9D: |
| 416 | case llvm::X86::R9W: |
| 417 | case llvm::X86::R9B: |
| 418 | return X64Reg_R9; |
| 419 | case llvm::X86::R10: |
| 420 | case llvm::X86::R10D: |
| 421 | case llvm::X86::R10W: |
| 422 | case llvm::X86::R10B: |
| 423 | return X64Reg_R10; |
| 424 | case llvm::X86::R11: |
| 425 | case llvm::X86::R11D: |
| 426 | case llvm::X86::R11W: |
| 427 | case llvm::X86::R11B: |
| 428 | return X64Reg_R11; |
| 429 | case llvm::X86::R12: |
| 430 | case llvm::X86::R12D: |
| 431 | case llvm::X86::R12W: |
| 432 | case llvm::X86::R12B: |
| 433 | return X64Reg_R12; |
| 434 | case llvm::X86::R13: |
no outgoing calls
no test coverage detected