| 8456 | } |
| 8457 | |
| 8458 | void BeMCContext::DoRegAssignPass() |
| 8459 | { |
| 8460 | BP_ZONE("BeMCContext::DoRegAssignPass"); |
| 8461 | |
| 8462 | bool generateLiveness = true; |
| 8463 | // |
| 8464 | if (generateLiveness) |
| 8465 | { |
| 8466 | for (auto& node : mColorizer.mNodes) |
| 8467 | { |
| 8468 | node.mEdges.Clear(); |
| 8469 | } |
| 8470 | mColorizer.Prepare(); |
| 8471 | GenerateLiveness(); |
| 8472 | } |
| 8473 | else |
| 8474 | { |
| 8475 | mColorizer.Prepare(); |
| 8476 | } |
| 8477 | |
| 8478 | mColorizer.GenerateRegCosts(); |
| 8479 | // |
| 8480 | { |
| 8481 | BP_ZONE("BeMCContext::DoRegAssignPass:ints"); |
| 8482 | mColorizer.AssignRegs(BeMCColorizer::RegKind_Ints); |
| 8483 | } |
| 8484 | // |
| 8485 | { |
| 8486 | BP_ZONE("BeMCContext::DoRegAssignPass:float"); |
| 8487 | mColorizer.AssignRegs(BeMCColorizer::RegKind_Floats); |
| 8488 | } |
| 8489 | |
| 8490 | #ifdef _DEBUG |
| 8491 | BF_ASSERT(mColorizer.Validate()); |
| 8492 | |
| 8493 | for (int vregIdx = 0; vregIdx < (int)mVRegInfo.size(); vregIdx++) |
| 8494 | { |
| 8495 | auto vregInfo = mVRegInfo[vregIdx]; |
| 8496 | if (vregInfo->mRefCount == 0) |
| 8497 | continue; |
| 8498 | if ((vregInfo->mIsRetVal) && (mCompositeRetVRegIdx != -1) && (vregIdx != mCompositeRetVRegIdx)) |
| 8499 | continue; |
| 8500 | if ((vregInfo->mForceReg) && (!vregInfo->mRelTo) && (vregInfo->mReg == X64Reg_None)) |
| 8501 | { |
| 8502 | SoftFail("Failed to assign register to ForceReg vreg"); |
| 8503 | } |
| 8504 | if (vregInfo->mDisableRAX) |
| 8505 | { |
| 8506 | BF_ASSERT(ResizeRegister(vregInfo->mReg, 8) != X64Reg_RAX); |
| 8507 | } |
| 8508 | if (vregInfo->mDisableRDX) |
| 8509 | { |
| 8510 | BF_ASSERT(ResizeRegister(vregInfo->mReg, 8) != X64Reg_RDX); |
| 8511 | } |
| 8512 | if (vregInfo->mDisableR11) |
| 8513 | { |
| 8514 | BF_ASSERT(ResizeRegister(vregInfo->mReg, 8) != X64Reg_R11); |
| 8515 | } |
nothing calls this directly
no test coverage detected