Register type. Provides a unique type that can be used to identify a register or its view.

A simple non-reference counted string that uses small string optimization (SSO). This string has 3 allocation possibilities: 1. Small - embedded

Base class for all memory operands. The data is split into the following parts: - BASE - Base register or label - requires 36 bits total. 4 bits are

Vector register (AArch64).

Operand array, mostly used for code generation that uses SIMD. Can hold up to `kMaxSize` registers, however, the number of actual registers is dynami

Unified physical or virtual register operand.

Represents ARM immediate shift operation type and value.

Floating point mode is used in places that are generic and implement various functionality that needs more than a single instruction. Typically implem

Memory operand (AArch64).

Vector register width.

Data alignment.

Label (jump target or data location). Label represents a location in code typically used as a jump target, but may be also a reference to some data o

Work register identifier (RA). Work register is an actual virtual register that is used by the function and subject to register allocation.

Vector operand array. Used to model SIMD code generation where the code generator can use up to \ref OpArray::kMaxSize registers per `VecArray`. The

List of physical registers (base). \note List of registers is only used by some ARM instructions at the moment.

AsmJit error code.

Unified vector register (also acts as a base class for architecture specific vector registers).

Unified general purpose register (also acts as a base class for architecture specific GP registers).

Instruction options. Instruction options complement instruction identifier and attributes.

Instruction with `[vec, vec]` operands. Describes vector arithmetic that has one destination and one source. \note For convenience, the second opera

Vector element type (AArch64).

Broadcast width.

Only used to lookup a label from `_named_labels`.

Virtual memory access and mmap-specific flags.

Basic block identifier (RA).

Count of live registers, per group.

Registers mask.

Shift operation predicate (ARM) describes either SHIFT or EXTEND operation. \note The constants are AsmJit specific. The first 5 values describe real

Base class used by \ref ArenaHash template

Represents an environment, which is usually related to a \ref Target. Environment has usually an 'arch-subarch-vendor-os-abi' format, which is someti

Function signature. Contains information about a function return type, count of arguments, and their TypeIds. Function signature is a low level struc

Memory offset mode. Describes either fixed, pre-index, or post-index offset modes.

Span that contains start (a) and end (b).

Count of virtual or physical registers per group. \note This class uses 8-bit integers to represent counters, it's only used in places where this is

Provides mapping that can be used to fast index architecture register groups.

Information associated with each instruction, propagated to blocks, loops, and the whole function. This information can be used to do minor decisions

A predicate that can be used as an immediate value with VPTERNLOG[D|Q] instruction. There are 3 inputs to the instruction (\ref kA, \ref kB, \ref kC)

Flags associated with a virtual register \ref VirtReg.