MemOperand represents the addressing mode of a load or store instruction.

MemOperand represents the addressing mode of a load or store instruction. Usage: <instr> <Rt> , <MemOperand> where <instr> is the instruction to use

Some CPURegister methods can return Register or VRegister types, so we need to declare them in advance.

Lists of registers.

Operand.

This an abstraction that can represent a register or memory location. The `MacroAssembler` provides helpers to move data between generic operands.

A representation of the set of features known to be supported by the target device. Each feature is represented by a simple boolean flag. - When the

Encodes an immediate value for operands. Note: Immediates can be 64b on x86-64 for certain instructions, but are often restricted to 32b. Note: As w

Representation of a vector register, with typed getters and setters for lanes and additional information to represent lane state.

Internal simulation class used solely by the simulator to provide an abstraction layer for any half-precision arithmetic.

Operand represents generic set of arguments to pass to an instruction. Usage: <instr> <Rd> , <Operand> where <instr> is the instruction to use (e.g.

The proper way to initialize a simulated system register (such as NZCV) is as follows: SimSystemRegister nzcv = SimSystemRegister::DefaultValueFor(NZC

Wrapper class for passing FP16 values through the assembler. This is purely to aid with type checking/casting.

Use this scope when you need a one-to-one mapping between methods and instructions. This scope will: - Do the same as `EmissionCheckScope`. - Block ac

Class describing the AArch64 procedure call standard, as defined in "ARM Procedure Call Standard for the ARM 64-bit Architecture (AArch64)", release 1

Add/sub with carry.

Assembler fixups are positions in generated code that require processing after the code has been copied to executable memory. This includes building r

Atomic memory.