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hub / github.com/Vector35/binaryninja-api / get_multireg_operand

Function get_multireg_operand

arch/arm64/disassembler/format.c:311–349  ·  view source on GitHub ↗

Source from the content-addressed store, hash-verified

309}
310
311uint32_t get_multireg_operand(const InstructionOperand *operand, char *result, uint32_t result_sz)
312{
313 char lane_str[32] = {0};
314 char reg_str[4][32];
315 uint32_t elem_n;
316 int rc;
317 memset(&reg_str, 0, sizeof(reg_str));
318
319 for (elem_n = 0; elem_n < 4 && operand->reg[elem_n] != REG_NONE; elem_n++)
320 if (get_register(operand, elem_n, reg_str[elem_n], 32) != 0)
321 return FAILED_TO_DISASSEMBLE_OPERAND;
322
323 if(operand->laneUsed)
324 snprintf(lane_str, sizeof(lane_str), "[%d]", operand->lane);
325
326 switch (elem_n)
327 {
328 case 1:
329 rc = snprintf(result, result_sz, "{%s}%s",
330 reg_str[0], lane_str);
331 break;
332 case 2:
333 rc = snprintf(result, result_sz, "{%s, %s}%s",
334 reg_str[0], reg_str[1], lane_str);
335 break;
336 case 3:
337 rc = snprintf(result, result_sz, "{%s, %s, %s}%s",
338 reg_str[0], reg_str[1], reg_str[2], lane_str);
339 break;
340 case 4:
341 rc = snprintf(result, result_sz, "{%s, %s, %s, %s}%s",
342 reg_str[0], reg_str[1], reg_str[2], reg_str[3], lane_str);
343 break;
344 default:
345 return FAILED_TO_DISASSEMBLE_OPERAND;
346 }
347
348 return rc < 0 ? FAILED_TO_DISASSEMBLE_OPERAND : DISASM_SUCCESS;
349}
350
351uint32_t get_shifted_immediate(const InstructionOperand *instructionOperand, char *outBuffer, uint32_t outBufferSize, uint32_t type)
352{

Callers 1

aarch64_disassembleFunction · 0.85

Calls 1

get_registerFunction · 0.70

Tested by

no test coverage detected