An immediate doubleword value used for instructions whose operand-size attribute is 32 bits. It allows the use of a number between +2,147,483,

A YMM register. The 256-bit YMM registers are: YMM0 through YMM7; YMM8 through YMM15 are available using REX.R in 64-bit mode. */

One of the doubleword general-purpose registers: EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI; or one of the doubleword registers (R8D - R15D) available

One of the quadword general-purpose registers: RAX, RBX, RCX, RDX, RDI, RSI, RBP, RSP, R8–R15. These are available when using REX.R and 64-bit mod

An XMM register. The 128-bit XMM registers are: XMM0 through XMM7; XMM8 through XMM15 are available using REX.R in 64-bit mode. */

One of the word general-purpose registers: AX, CX, DX, BX, SP, BP, SI, DI; or one of the word registers (R8W - R15W) available when using REX.R an

One of the byte general-purpose registers: BPL, SPL, DIL and SIL; or one of the byte registers (R8B - R15B) available when using REX.R and 64-bit

An MMX register. The 64-bit MMX registers are: MM0 through MM7. */

The ith element from the top of the FPU register stack (i = 0 through 7). */

One of the byte general-purpose registers: AH, CH, DH, BH. */

A segment register. The segment register bit assignments are ES = 0, CS = 1, SS = 2, DS = 3, FS = 4, and GS = 5. */

A taken/not-taken hint for conditional jumps. */

An immediate byte value. The imm8 symbol is a signed number between –128 and +127 inclusive. For instructions in which imm8 is combined with a

One of the byte general-purpose registers: AL, CL, DL, BL. */

The byte general-purpose register AL. */

An in-memory assembler. This class can be thought of as an expert user of the Function api. */

The word general-purpose register AX. */

The byte general-purpose register CL. */

The word general-purpose register DX. */

The doubleword general-purpose register EAX. */

Far instruction variant. */

The FPU Data register. */

The FPU Instruction register. */

The FPU Opcode regiter. */

The segment register FS. */

The segment register GS. */

An immediate word value used for instructions whose operand-size attribute is 16 bits. This is a number between -32,768 and +32,767 inclusive. */

An immediate quadword value used for instructions whose operand-size attribute is 64 bits. The value allows the use of a number between +9,223

A symbolic representation of a Rel32. No Rel8 eqivalent is provided. */

A byte operand in memory, usually expressed as a variable or array name, but pointed to by the DS:(E)SI or ES:(E)DI registers. In 64-bit mode,

A simple memory variable (memory offset) of type byte. */

The immediate constant value one */

The 32-bit memory address override prefix: 0x66. */

The REX.w prefix: 0x48. */

The quadword general-purpose register RAX. */

A relative address within the same code segment as the instruction assembled. The rel32 symbol applies to instructions with an operand-size at

A relative address in the range from 128 bytes before the end of the instruction to 127 bytes after the end of the instruction. */

The instruction pointer register. */

The top element of the FPU register stack. */

The immediate constant value three */

The XMM register XMM0. */

The immediate constant value zero */

A static class for resolving hardware aliasing relationships. */

A sequence of Instructions. In addition to the methods defined below, this class supports all of the behvaior of an STL sequence container. */

Predefined assembler constants. Direct access to the object constructors is disallowed in general. */

An EFLAGS register bit. */

An environment register bit. */

An environment register. */

A memory operand containing a far pointer composed of two numbers. The number to the left of the colon corresponds to the pointer's segment se

A memory operand containing a far pointer composed of two numbers. The number to the left of the colon corresponds to the pointer's segment se

A memory operand containing a far pointer composed of two numbers. The number to the left of the colon corresponds to the pointer's segment se

CPUID Feature Flags. */

An FPU control register bit. */

An FPU status register bit. */

An FPU tag register. */

An executable hex buffer. Supports zero to six argument calling conventions. In general, a function can be called with arguments of any type w

An immediate value. */

A hardware instruction; operands are stored in intel order with target given first. The implementation of this class is similar to the java im

A 108 byte operand in memory. */

A memory double quadword operand in memory. */

A word operand in memory, usually expressed as a variable or array name, but pointed to by the DS:(E)SI or ES:(E)DI registers. This nomenclature i

A word integer operand in memory. This symbol designates integers that are used as operands for x87 FPU integer instructions. */

A 32-byte operand in memory. This nomenclature is used only with AVX instructions. */

A 28 byte operand in memory. */

A 2 byte operand in memory. */

A doubleword operand in memory, usually expressed as a variable or array name, but pointed to by the DS:(E)SI or ES:(E)DI registers. This nome

A single-precision floating-point operand in memory. This symbol designates floating-point values that are used as operands for x87 FPU floating-p

A doubleword integer operand in memory. This symbol designates integers that are used as operands for x87 FPU integer instructions. */

A 512 byte operand in memory. */

A memory quadword operand in memory. */

A double-precision floating-point operand in memory. This symbol designates floating-point values that are used as operands for x87 FPU floating-p

A quadword integer operand in memory. This symbol designates integers that are used as operands for x87 FPU integer instructions. */

A double extended-precision binary-coded-decimaly operand in memory. */

A double extended-precision floating-point operand in memory. This symbol designates floating-point values that are used as operands for x87 FPU

A modifier used to distinguish between mnemonics. These are non-standard operands which we have introduced to disambiguate parts of the intel x86_

A simple memory variable. This is the only operand type to use both underlying value variables. */

A simple memory variable (memory offset) of type word. */

A simple memory variable (memory offset) of type doubleword. */

A simple memory variable (memory offset) of type quadword. */

An MXCSR register bit. */

An instruction mnemonic. */

Base operand type. This class is provisioned with enough storage space for an operand of any type. This prevents object slicing from losing in

A general-purpose register. */

A compact implementation of a bit set for registers. */