| 1410 | } |
| 1411 | |
| 1412 | int8_t mcp2518fd::mcp2518fd_ReceiveMessageGet(CAN_FIFO_CHANNEL channel, |
| 1413 | CAN_RX_MSGOBJ *rxObj, |
| 1414 | uint8_t *rxd, uint8_t nBytes) { |
| 1415 | uint8_t n = 0; |
| 1416 | uint8_t i = 0; |
| 1417 | uint16_t a; |
| 1418 | uint32_t fifoReg[3]; |
| 1419 | REG_CiFIFOCON ciFifoCon; |
| 1420 | REG_CiFIFOUA ciFifoUa; |
| 1421 | int8_t spiTransferError = 0; |
| 1422 | |
| 1423 | // Get FIFO registers |
| 1424 | a = cREGADDR_CiFIFOCON + (channel * CiFIFO_OFFSET); |
| 1425 | |
| 1426 | spiTransferError = mcp2518fd_ReadWordArray(a, fifoReg, 3); |
| 1427 | if (spiTransferError) { |
| 1428 | return -1; |
| 1429 | } |
| 1430 | |
| 1431 | // Check that it is a receive buffer |
| 1432 | ciFifoCon.word = fifoReg[0]; |
| 1433 | ciFifoCon.txBF.TxEnable = 0; |
| 1434 | if (ciFifoCon.txBF.TxEnable) { |
| 1435 | return -2; |
| 1436 | } |
| 1437 | |
| 1438 | // Get address |
| 1439 | ciFifoUa.word = fifoReg[2]; |
| 1440 | #ifdef USERADDRESS_TIMES_FOUR |
| 1441 | a = 4 * ciFifoUa.bF.UserAddress; |
| 1442 | #else |
| 1443 | a = ciFifoUa.bF.UserAddress; |
| 1444 | #endif |
| 1445 | a += cRAMADDR_START; |
| 1446 | |
| 1447 | // Number of bytes to read |
| 1448 | n = nBytes + 8; // Add 8 header bytes |
| 1449 | |
| 1450 | if (ciFifoCon.rxBF.RxTimeStampEnable) { |
| 1451 | n += 4; // Add 4 time stamp bytes |
| 1452 | } |
| 1453 | |
| 1454 | // Make sure we read a multiple of 4 bytes from RAM |
| 1455 | if (n % 4) { |
| 1456 | n = n + 4 - (n % 4); |
| 1457 | } |
| 1458 | |
| 1459 | // Read rxObj using one access |
| 1460 | uint8_t ba[MAX_MSG_SIZE]; |
| 1461 | |
| 1462 | if (n > MAX_MSG_SIZE) { |
| 1463 | n = MAX_MSG_SIZE; |
| 1464 | } |
| 1465 | |
| 1466 | spiTransferError = mcp2518fd_ReadByteArray(a, ba, n); |
| 1467 | if (spiTransferError) { |
| 1468 | return -3; |
| 1469 | } |
nothing calls this directly
no outgoing calls
no test coverage detected