| 84 | } |
| 85 | |
| 86 | static void cpu_loops_per_tick_init(void) |
| 87 | { |
| 88 | rt_ubase_t offset; |
| 89 | volatile rt_ubase_t freq, step, cycles_end1, cycles_end2; |
| 90 | volatile rt_uint32_t cycles_count1 = 0, cycles_count2 = 0; |
| 91 | |
| 92 | rt_hw_sysreg_read(cntfrq_el0, freq); |
| 93 | step = freq / RT_TICK_PER_SECOND; |
| 94 | |
| 95 | cycles_end1 = cpu_get_cycles() + step; |
| 96 | |
| 97 | while (cpu_get_cycles() < cycles_end1) |
| 98 | { |
| 99 | __asm__ volatile ("nop"); |
| 100 | __asm__ volatile ("add %0, %0, #1":"=r"(cycles_count1)); |
| 101 | } |
| 102 | |
| 103 | cycles_end2 = cpu_get_cycles() + step; |
| 104 | |
| 105 | while (cpu_get_cycles() < cycles_end2) |
| 106 | { |
| 107 | __asm__ volatile ("add %0, %0, #1":"=r"(cycles_count2)); |
| 108 | } |
| 109 | |
| 110 | if ((rt_int32_t)(cycles_count2 - cycles_count1) > 0) |
| 111 | { |
| 112 | offset = cycles_count2 - cycles_count1; |
| 113 | } |
| 114 | else |
| 115 | { |
| 116 | /* Impossible, but prepared for any eventualities */ |
| 117 | offset = cycles_count2 / 4; |
| 118 | } |
| 119 | |
| 120 | loops_per_tick[rt_hw_cpu_id()] = offset; |
| 121 | } |
| 122 | |
| 123 | static void cpu_us_delay(rt_uint32_t us) |
| 124 | { |
no test coverage detected