| 144 | } |
| 145 | |
| 146 | rt_inline void cpu_info_init(void) |
| 147 | { |
| 148 | int i = 0; |
| 149 | rt_uint64_t mpidr; |
| 150 | struct rt_ofw_node *np; |
| 151 | |
| 152 | /* get boot cpu info */ |
| 153 | rt_hw_sysreg_read(mpidr_el1, mpidr); |
| 154 | |
| 155 | rt_ofw_foreach_cpu_node(np) |
| 156 | { |
| 157 | rt_uint64_t hwid = rt_ofw_get_cpu_hwid(np, 0); |
| 158 | |
| 159 | if ((mpidr & MPIDR_AFFINITY_MASK) != hwid) |
| 160 | { |
| 161 | /* Only save affinity and res make smp boot can check */ |
| 162 | hwid |= 1ULL << 31; |
| 163 | } |
| 164 | else |
| 165 | { |
| 166 | hwid = mpidr; |
| 167 | } |
| 168 | |
| 169 | cpu_np[i] = np; |
| 170 | rt_cpu_mpidr_table[i] = hwid; |
| 171 | |
| 172 | rt_ofw_data(np) = (void *)hwid; |
| 173 | |
| 174 | for (int idx = 0; idx < RT_ARRAY_SIZE(cpu_ops); ++idx) |
| 175 | { |
| 176 | struct cpu_ops_t *ops = cpu_ops[idx]; |
| 177 | |
| 178 | if (ops->cpu_init) |
| 179 | { |
| 180 | ops->cpu_init(i, np); |
| 181 | } |
| 182 | } |
| 183 | |
| 184 | if (++i >= RT_CPUS_NR) |
| 185 | { |
| 186 | break; |
| 187 | } |
| 188 | } |
| 189 | |
| 190 | rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, rt_cpu_mpidr_table, sizeof(rt_cpu_mpidr_table)); |
| 191 | |
| 192 | #ifdef RT_USING_HWTIMER |
| 193 | cpu_loops_per_tick_init(); |
| 194 | |
| 195 | if (!rt_device_hwtimer_us_delay) |
| 196 | { |
| 197 | rt_device_hwtimer_us_delay = &cpu_us_delay; |
| 198 | } |
| 199 | #endif /* RT_USING_HWTIMER */ |
| 200 | } |
| 201 | |
| 202 | void rt_hw_common_setup(void) |
| 203 | { |
no test coverage detected