Function rt_hw_mmu_map

libcpu/aarch64/common/mmu.c:277–347

}

void *rt_hw_mmu_map(rt_aspace_t aspace, void *v_addr, void *p_addr, size_t size,
                    size_t attr)
{
    int ret = -1;

    void *unmap_va = v_addr;
    size_t remaining_sz = size;
    size_t stride;
    int (*mapper)(unsigned long *lv0_tbl, void *vaddr, void *paddr, unsigned long attr);

    RT_ASSERT(!(size & ARCH_PAGE_MASK));

    while (remaining_sz)
    {
        if (((rt_ubase_t)v_addr & ARCH_SECTION_MASK) ||
            ((rt_ubase_t)p_addr & ARCH_SECTION_MASK) ||
            (remaining_sz < ARCH_SECTION_SIZE))
        {
            /* legacy 4k mapping */
            stride = ARCH_PAGE_SIZE;
            mapper = _kernel_map_4K;
        }
        else
        {
            /* 2m huge page */
            stride = ARCH_SECTION_SIZE;
            mapper = _kernel_map_2M;
        }

        /* check aliasing */
        #ifdef RT_DEBUGGING_ALIASING
        #define _ALIAS_OFFSET(addr) ((long)(addr) & (RT_PAGE_AFFINITY_BLOCK_SIZE - 1))
        if (rt_page_is_member((rt_base_t)p_addr) && _ALIAS_OFFSET(v_addr) != _ALIAS_OFFSET(p_addr))
        {
            LOG_W("Possibly aliasing on va(0x%lx) to pa(0x%lx)", v_addr, p_addr);
            rt_backtrace();
            RT_ASSERT(0);
        }
        #endif /* RT_DEBUGGING_ALIASING */

        MM_PGTBL_LOCK(aspace);
        ret = mapper(aspace->page_table, v_addr, p_addr, attr);
        MM_PGTBL_UNLOCK(aspace);

        if (ret != 0)
        {
            /* other types of return value are taken as programming error */
            RT_ASSERT(ret == MMU_MAP_ERROR_NOPAGE);
            /* error, undo map */
            while (unmap_va != v_addr)
            {
                MM_PGTBL_LOCK(aspace);
                _kenrel_unmap_4K(aspace->page_table, (void *)unmap_va);
                MM_PGTBL_UNLOCK(aspace);
                unmap_va = (char *)unmap_va + stride;
            }
            break;
        }