| 71 | }; |
| 72 | |
| 73 | static void _kenrel_unmap_4K(unsigned long *lv0_tbl, void *v_addr) |
| 74 | { |
| 75 | int level; |
| 76 | unsigned long va = (unsigned long)v_addr; |
| 77 | unsigned long *cur_lv_tbl = lv0_tbl; |
| 78 | unsigned long page; |
| 79 | unsigned long off; |
| 80 | struct mmu_level_info level_info[4]; |
| 81 | int ref; |
| 82 | int level_shift = MMU_ADDRESS_BITS; |
| 83 | unsigned long *pos; |
| 84 | |
| 85 | rt_memset(level_info, 0, sizeof level_info); |
| 86 | for (level = 0; level < MMU_TBL_LEVEL_NR; level++) |
| 87 | { |
| 88 | off = (va >> level_shift); |
| 89 | off &= MMU_LEVEL_MASK; |
| 90 | page = cur_lv_tbl[off]; |
| 91 | if (!(page & MMU_TYPE_USED)) |
| 92 | { |
| 93 | break; |
| 94 | } |
| 95 | if ((page & MMU_TYPE_MASK) == MMU_TYPE_BLOCK) |
| 96 | { |
| 97 | break; |
| 98 | } |
| 99 | /* next table entry in current level */ |
| 100 | level_info[level].pos = cur_lv_tbl + off; |
| 101 | cur_lv_tbl = (unsigned long *)(page & MMU_ADDRESS_MASK); |
| 102 | cur_lv_tbl = (unsigned long *)((unsigned long)cur_lv_tbl - PV_OFFSET); |
| 103 | level_info[level].page = cur_lv_tbl; |
| 104 | level_shift -= MMU_LEVEL_SHIFT; |
| 105 | } |
| 106 | |
| 107 | level = MMU_TBL_PAGE_4k_LEVEL; |
| 108 | pos = level_info[level].pos; |
| 109 | if (pos) |
| 110 | { |
| 111 | *pos = (unsigned long)RT_NULL; |
| 112 | rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, pos, sizeof(void *)); |
| 113 | } |
| 114 | level--; |
| 115 | |
| 116 | while (level >= 0) |
| 117 | { |
| 118 | pos = level_info[level].pos; |
| 119 | if (pos) |
| 120 | { |
| 121 | void *cur_page = level_info[level].page; |
| 122 | ref = rt_page_ref_get(cur_page, 0); |
| 123 | if (ref == 1) |
| 124 | { |
| 125 | *pos = (unsigned long)RT_NULL; |
| 126 | rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, pos, sizeof(void *)); |
| 127 | } |
| 128 | rt_pages_free(cur_page, 0); |
| 129 | } |
| 130 | else |
no test coverage detected