Function rt_pci_setup_device

components/drivers/pci/probe.c:304–397

}

rt_err_t rt_pci_setup_device(struct rt_pci_device *pdev)
{
    rt_uint8_t pos;
    rt_uint32_t class = 0;
    struct rt_pci_host_bridge *host_bridge;

    if (!pdev)
    {
        return -RT_EINVAL;
    }

    if (!(host_bridge = rt_pci_find_host_bridge(pdev->bus)))
    {
        return -RT_EINVAL;
    }

    rt_pci_ofw_device_init(pdev);

    rt_pci_read_config_u32(pdev, PCIR_REVID, &class);

    pdev->revision = class & 0xff;
    pdev->class = class >> 8;   /* Upper 3 bytes */
    rt_pci_read_config_u8(pdev, PCIR_HDRTYPE, &pdev->hdr_type);

    /* Clear errors left from system firmware */
    rt_pci_write_config_u16(pdev, PCIR_STATUS, 0xffff);

    if (pdev->hdr_type & 0x80)
    {
        pdev->multi_function = RT_TRUE;
    }
    pdev->hdr_type &= PCIM_HDRTYPE;

    if (pci_intx_mask_broken(pdev))
    {
        pdev->broken_intx_masking = RT_TRUE;
    }

    rt_dm_dev_set_name(&pdev->parent, "%04x:%02x:%02x.%u", rt_pci_domain(pdev),
            pdev->bus->number, RT_PCI_SLOT(pdev->devfn), RT_PCI_FUNC(pdev->devfn));

    switch (pdev->hdr_type)
    {
    case PCIM_HDRTYPE_NORMAL:
        if (class == PCIS_BRIDGE_PCI)
        {
            goto error;
        }
        pci_read_irq(pdev);
        rt_pci_device_alloc_resource(host_bridge, pdev);
        rt_pci_read_config_u16(pdev, PCIR_SUBVEND_0, &pdev->subsystem_vendor);
        rt_pci_read_config_u16(pdev, PCIR_SUBDEV_0, &pdev->subsystem_device);
        break;

    case PCIM_HDRTYPE_BRIDGE:
        pci_read_irq(pdev);
        rt_pci_device_alloc_resource(host_bridge, pdev);
        pos = rt_pci_find_capability(pdev, PCIY_SUBVENDOR);