| 265 | } |
| 266 | |
| 267 | static rt_ubase_t dma_pool_alloc(struct rt_dma_pool *pool, rt_size_t size) |
| 268 | { |
| 269 | rt_size_t bit, next_bit, end_bit, max_bits; |
| 270 | |
| 271 | size = RT_DIV_ROUND_UP(size, ARCH_PAGE_SIZE); |
| 272 | max_bits = pool->bits - size; |
| 273 | |
| 274 | rt_bitmap_for_each_clear_bit(pool->map, bit, max_bits) |
| 275 | { |
| 276 | end_bit = bit + size; |
| 277 | |
| 278 | for (next_bit = bit + 1; next_bit < end_bit; ++next_bit) |
| 279 | { |
| 280 | if (rt_bitmap_test_bit(pool->map, next_bit)) |
| 281 | { |
| 282 | bit = next_bit; |
| 283 | goto _next; |
| 284 | } |
| 285 | } |
| 286 | |
| 287 | if (next_bit == end_bit) |
| 288 | { |
| 289 | while (next_bit --> bit) |
| 290 | { |
| 291 | rt_bitmap_set_bit(pool->map, next_bit); |
| 292 | } |
| 293 | |
| 294 | return pool->start + bit * ARCH_PAGE_SIZE; |
| 295 | } |
| 296 | _next: |
| 297 | } |
| 298 | |
| 299 | return RT_NULL; |
| 300 | } |
| 301 | |
| 302 | static void dma_pool_free(struct rt_dma_pool *pool, rt_ubase_t offset, rt_size_t size) |
| 303 | { |
| 304 | rt_size_t bit = (offset - pool->start) / ARCH_PAGE_SIZE, end_bit; |
| 305 | |
| 306 | size = RT_DIV_ROUND_UP(size, ARCH_PAGE_SIZE); |
| 307 | end_bit = bit + size; |
| 308 | |
| 309 | for (; bit < end_bit; ++bit) |
| 310 | { |
| 311 | rt_bitmap_clear_bit(pool->map, bit); |
| 312 | } |
| 313 | } |
| 314 | |
| 315 | static void *dma_alloc(struct rt_device *dev, rt_size_t size, |
| 316 | rt_ubase_t *dma_handle, rt_ubase_t flags) |
| 317 | { |
| 318 | void *dma_buffer = RT_NULL; |
| 319 | struct rt_dma_pool *pool; |
| 320 | |
| 321 | region_pool_lock(); |
| 322 | |
| 323 | rt_list_for_each_entry(pool, &dma_pool_nodes, list) |
| 324 | { |
no test coverage detected