Function Gmac_WritePHYRegister

bsp/ft2004/libraries/bsp/ft_gmac/ft_gmac_hw.c:30–56

#define GMAC_HW_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(GMAC_HW_DEBUG_TAG, format, ##__VA_ARGS__)

s32 Gmac_WritePHYRegister(FGmac_Config_t *Config, u16 PHYReg, u32 RegValue)
{
    u32 TmpReg;
    u32 Wait_Counter = 0;

    TmpReg = Ft_in32(Config->BaseAddress + GMAC_MII_ADDR_OFFSET);

    TmpReg |= GMAC_MII_ADDR_CR(Config->clkMDC);
    TmpReg |= GMAC_MII_ADDR_PA(Config->PhyAddr); /* Set the PHY device address   */
    TmpReg |= GMAC_MII_ADDR_GR(PHYReg);          /* Set the PHY register address */
    TmpReg |= GMAC_MII_ADDR_GW;                  /*  Set the write mode   */
    TmpReg |= GMAC_MII_ADDR_GB;                  /* Set the MII Busy bit */

    Ft_out32(Config->BaseAddress + GMAC_MII_DATA_OFFSET, RegValue);
    Ft_out32(Config->BaseAddress + GMAC_MII_ADDR_OFFSET, TmpReg);

    /* Check for the Busy flag */
    while ((Ft_in32(Config->BaseAddress + GMAC_MII_ADDR_OFFSET) & GMAC_MII_ADDR_GB) == GMAC_MII_ADDR_GB)
    {
        if (10000000 <= ++Wait_Counter)
        {
            GMAC_HW_DEBUG_E("Gmac_WritePHYRegister FST_ERROR_COUNT_MAX \r\n");
            return FST_ERROR_COUNT_MAX;
        }
    }
    return FST_SUCCESS;
}

s32 FGmac_ReadPHYRegister(FGmac_Config_t *Config, u16 PHYReg, u32 *RegValue)
{