Function FGmac_ReadPHYRegister

bsp/ft2004/libraries/bsp/ft_gmac/ft_gmac_hw.c:58–93

}

s32 FGmac_ReadPHYRegister(FGmac_Config_t *Config, u16 PHYReg, u32 *RegValue)
{
    u32 TmpReg;
    u32 Wait_Counter = 0;

    TmpReg = 0;
    TmpReg |= GMAC_MII_ADDR_CR(Config->clkMDC);
    TmpReg |= GMAC_MII_ADDR_PA(Config->PhyAddr); /* Set the PHY device address   */
    TmpReg |= GMAC_MII_ADDR_GR(PHYReg);          /* Set the PHY register address */
    TmpReg &= ~GMAC_MII_ADDR_GW;                 /*  Set the read mode   */
    TmpReg |= GMAC_MII_ADDR_GB;                  /* Set the MII Busy bit */

    while ((Ft_in32(Config->BaseAddress + GMAC_MII_ADDR_OFFSET) & GMAC_MII_ADDR_GB) == GMAC_MII_ADDR_GB)
    {
        if (10000000 <= ++Wait_Counter)
        {
            GMAC_HW_DEBUG_E("wait GMAC_MII_ADDR_GB is error \r\n");
            *RegValue = 0xffff;
            return FST_ERROR_COUNT_MAX;
        }
    }

    Ft_out32(Config->BaseAddress + GMAC_MII_ADDR_OFFSET, TmpReg);

    while ((Ft_in32(Config->BaseAddress + GMAC_MII_ADDR_OFFSET) & GMAC_MII_ADDR_GB) == GMAC_MII_ADDR_GB)
    {
        if (10000000 <= ++Wait_Counter)
        {
            GMAC_HW_DEBUG_E("wait GMAC_MII_ADDR_GB 2 is error \r\n");
            *RegValue = 0xffff;
            return FST_ERROR_COUNT_MAX;
        }
    }
    *RegValue = Ft_in32(Config->BaseAddress + GMAC_MII_DATA_OFFSET);
    return FST_SUCCESS;
}

static s32 FGmac_PhyAddrGet(FGmac_Config_t *Config)
{