| 134 | |
| 135 | |
| 136 | static void FGmac_MACDMAInit(FGmac_Config_t *Config) |
| 137 | { |
| 138 | u32 RegValue = 0; |
| 139 | Ft_assertVoid(FGmac_PhyAddrGet(Config) == FST_SUCCESS); |
| 140 | RegValue = Ft_in32(Config->BaseAddress + GMAC_CONTROL_OFFSET); |
| 141 | /* MACCR Configuration **************************************/ |
| 142 | /* Set the WD bit according to ETH Watchdog value */ |
| 143 | /* Set the JD: bit according to ETH Jabber value */ |
| 144 | /* Set the IFG bit according to ETH InterFrameGap value */ |
| 145 | /* Set the DCRS bit according to ETH CarrierSense value */ |
| 146 | /* Set the FES bit according to ETH Speed value */ |
| 147 | /* Set the DO bit according to ETH ReceiveOwn value */ |
| 148 | /* Set the LM bit according to ETH LoopbackMode value */ |
| 149 | /* Set the DM bit according to ETH Mode value */ |
| 150 | /* Set the IPCO bit according to ETH ChecksumOffload value */ |
| 151 | /* Set the DR bit according to ETH RetryTransmission value */ |
| 152 | /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */ |
| 153 | /* Set the BL bit according to ETH BackOffLimit value */ |
| 154 | /* Set the DC bit according to ETH DeferralCheck value */ |
| 155 | RegValue &= ~GMAC_CONTROL_WD; |
| 156 | RegValue &= ~GMAC_CONTROL_JD; |
| 157 | RegValue |= GMAC_CONTROL_IFG(0); |
| 158 | RegValue &= ~GMAC_CONTROL_DCRS; |
| 159 | RegValue &= ~GMAC_CONTROL_DO; |
| 160 | RegValue &= ~GMAC_CONTROL_LM; |
| 161 | if (Config->ChecksumMode) |
| 162 | { |
| 163 | RegValue |= GMAC_CONTROL_IPC; |
| 164 | } |
| 165 | else |
| 166 | { |
| 167 | RegValue &= ~GMAC_CONTROL_IPC; |
| 168 | } |
| 169 | |
| 170 | RegValue |= GMAC_CONTROL_DR; |
| 171 | RegValue &= ~GMAC_CONTROL_ACS; |
| 172 | RegValue |= GMAC_CONTROL_BL(0); |
| 173 | RegValue &= ~GMAC_CONTROL_DC; |
| 174 | if (Config->DuplexMode == GMAC_MODE_FULLDUPLEX) |
| 175 | { |
| 176 | RegValue |= GMAC_CONTROL_DM; |
| 177 | } |
| 178 | else |
| 179 | { |
| 180 | RegValue &= ~GMAC_CONTROL_DM; |
| 181 | } |
| 182 | |
| 183 | RegValue &= ~GMAC_CONTROL_FES; |
| 184 | Ft_out32(Config->BaseAddress + GMAC_CONTROL_OFFSET, RegValue); |
| 185 | Ft_GenericTimer_UsDelay(PHY_CONFIG_DELAY_US); |
| 186 | |
| 187 | /*----------------------- GMAC MACFFR Configuration --------------------*/ |
| 188 | /* Set the RA bit according to ETH ReceiveAll value */ |
| 189 | /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */ |
| 190 | /* Set the PCF bit according to ETH PassControlFrames value */ |
| 191 | /* Set the DBF bit according to ETH BroadcastFramesReception value */ |
| 192 | /* Set the DAIF bit according to ETH DestinationAddrFilter value */ |
| 193 | /* Set the PR bit according to ETH PromiscuousMode value */ |
no test coverage detected