Function efm_eth_tx

bsp/efm32/drv_ethernet.c:844–915

/ * @brief * Packet transmission function * * @details * * @note * * @param[in] dev * Pointer to device descriptor * * @param[in] p * Pointer to packet buffer * * @return * Error code ******************************************************************************/

*   Error code
******************************************************************************/
rt_err_t efm_eth_tx(rt_device_t dev, struct pbuf* p)
{
    rt_uint8_t data;
    struct pbuf* q;

    /* Lock device */
    rt_sem_take(&ethLock, RT_WAITING_FOREVER);

    /* Disable interrupts */
    data = EIE_INTIE;
    efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIE, &data);

    /* Set write pointer to the start of TX buffer */
    efm_eth_writeReg(EWRPTL, TXSTART_INIT & 0xFF);
    efm_eth_writeReg(EWRPTH, TXSTART_INIT >> 8);
    /* Set buffer end pointer according to the packet size */
    efm_eth_writeReg(ETXNDL, (TXSTART_INIT + p->tot_len + 1) & 0xFF);
    efm_eth_writeReg(ETXNDH, (TXSTART_INIT + p->tot_len + 1) >> 8);

    /* Send write buffer command */
    data = 0x00;    /* Control byte */
    efm_eth_sendCmd(ENC28J60_WRITE_BUF_MEM, EFM32_NO_DATA, &data);
    /* Send data */
    for (q = p; q != NULL; q = q->next)
    {
        if (spi->write(spi, EFM32_NO_DATA, q->payload, q->len) == 0)
        {
            eth_debug("ETH: TX failed!\n");
            return -RT_ERROR;
        }
#ifdef EFM32_ETHERNET_DEBUG
        {
            rt_uint8_t *temp = (rt_uint8_t *)q->payload;
            rt_uint32_t i;

            eth_debug("ETH: ***** write TX (len %d) *****\n", p->len);
            for (i = 0; i < q->len; i += 8)
            {
                eth_debug("%02x %02x %02x %02x %02x %02x %02x %02x | %c %c %c %c %c %c %c %c\n",
                    temp[i], temp[i + 1], temp[i + 2], temp[i + 3],
                    temp[i + 4], temp[i + 5], temp[i + 6], temp[i + 7],
                    temp[i], temp[i + 1], temp[i + 2], temp[i + 3],
                    temp[i + 4], temp[i + 5], temp[i + 6], temp[i + 7]);
            }
        }
#endif
    }
    efm_eth_cs(0);
    /* Start TX */
    data = ECON1_TXRTS;
    efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, ECON1, &data);
    /* Errata 12 */
    if (efm_eth_readReg(EIR) & EIR_TXERIF)
    {
        efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, ECON1, &data);
        data = EIR_TXERIF;
        efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIR, &data);
        data = ECON1_TXRTS;