/ * @brief * Wait for ongoing sync of register(s) to low frequency domain to complete. * * @param[in] mask * Bitmask corresponding to SYNCBUSY register defined bits, indicating * registers that must complete any ongoing synchronization. ******************************************************************************/
| 412 | * registers that must complete any ongoing synchronization. |
| 413 | ******************************************************************************/ |
| 414 | __STATIC_INLINE void CMU_Sync(uint32_t mask) |
| 415 | { |
| 416 | /* Avoid deadlock if modifying the same register twice when freeze mode is */ |
| 417 | /* activated. */ |
| 418 | if (CMU->FREEZE & CMU_FREEZE_REGFREEZE) |
| 419 | return; |
| 420 | |
| 421 | /* Wait for any pending previous write operation to have been completed */ |
| 422 | /* in low frequency domain */ |
| 423 | while (CMU->SYNCBUSY & mask) |
| 424 | ; |
| 425 | } |
| 426 | |
| 427 | |
| 428 | /** @endcond */ |
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