Function CMU_FlashWaitStateControl

bsp/efm32/Libraries/emlib/src/em_cmu.c:152–213

/ * @brief * Configure flash access wait states in order to support given HFCORECLK * frequency. * * @param[in] hfcoreclk * HFCORECLK frequency that flash access wait states must be configured for. ******************************************************************************/

 *   HFCORECLK frequency that flash access wait states must be configured for.
 ******************************************************************************/
static void CMU_FlashWaitStateControl(uint32_t hfcoreclk)
{
  uint32_t cfg;

  cfg = MSC->READCTRL;

#if defined(_EFM32_GIANT_FAMILY)
  if (hfcoreclk > CMU_MAX_FREQ_1WS)
  {
    switch(cfg & _MSC_READCTRL_MODE_MASK)
    {
    case MSC_READCTRL_MODE_WS0SCBTP:
    case MSC_READCTRL_MODE_WS1SCBTP:
      cfg = (cfg & ~_MSC_READCTRL_MODE_MASK) | MSC_READCTRL_MODE_WS2SCBTP;
      break;
    case MSC_READCTRL_MODE_WS0:
    case MSC_READCTRL_MODE_WS1:
    default:
      cfg = (cfg & ~_MSC_READCTRL_MODE_MASK) | MSC_READCTRL_MODE_WS2;
      break;
    }
  }
#endif

  if ((hfcoreclk > CMU_MAX_FREQ_0WS) && (hfcoreclk <= CMU_MAX_FREQ_1WS))
  {
    switch (cfg & _MSC_READCTRL_MODE_MASK)
    {
#if defined(_EFM32_GIANT_FAMILY)
    case MSC_READCTRL_MODE_WS2SCBTP:
#endif
    case MSC_READCTRL_MODE_WS0SCBTP:
    case MSC_READCTRL_MODE_WS1SCBTP:
      cfg = (cfg & ~_MSC_READCTRL_MODE_MASK) | MSC_READCTRL_MODE_WS1SCBTP;
      break;

    default:
      cfg = (cfg & ~_MSC_READCTRL_MODE_MASK) | MSC_READCTRL_MODE_WS1;
      break;
    }
  }

  if (hfcoreclk <= CMU_MAX_FREQ_0WS)
  {
    switch (cfg & _MSC_READCTRL_MODE_MASK)
    {
#if defined(_EFM32_GIANT_FAMILY)
    case MSC_READCTRL_MODE_WS2SCBTP:
#endif
    case MSC_READCTRL_MODE_WS1SCBTP:
    case MSC_READCTRL_MODE_WS0SCBTP:
      cfg = (cfg & ~_MSC_READCTRL_MODE_MASK) | MSC_READCTRL_MODE_WS0SCBTP;
      break;

    default:
      cfg = (cfg & ~_MSC_READCTRL_MODE_MASK) | MSC_READCTRL_MODE_WS0;
      break;
    }