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Functions771 in github.com/RIP-Comm/clementine

⨍ Functions 771◇ Types & classes 120
↓ 1 callersMethoddrain_entries
Drain available entries from the channel and append to display. Limits processing to avoid blocking the UI.
ui/src/disassembler.rs:83
↓ 1 callersMethodemit_sample
Mix all channels into a stereo frame and push it.
emu/src/cpu/hardware/sound.rs:616
↓ 1 callersMethodexec_data_transfer
( &mut self, reg_list: u32, indexing: Indexing, address: &mut usize, o
emu/src/cpu/arm/operations.rs:1054
↓ 1 callersMethodexecute_batch
Execute a batch of CPU cycles. Runs up to `CYCLES_PER_BATCH` cycles, then returns to check for commands. Frames and state are sent automatically when
ui/src/emu_thread.rs:530
↓ 1 callersMethodfetch_arm
(&mut self)
emu/src/cpu/arm7tdmi.rs:252
↓ 1 callersMethodfetch_thumb
(&mut self)
emu/src/cpu/arm7tdmi.rs:272
↓ 1 callersMethodflash_id
Flash manufacturer/device ID pair reported in ID mode.
emu/src/cpu/hardware/internal_memory.rs:102
↓ 1 callersMethodflash_write
(&mut self, offset: usize, value: u8)
emu/src/cpu/hardware/internal_memory.rs:548
↓ 1 callersMethodformat
(&self)
emu/src/cpu/mod.rs:86
↓ 1 callersMethodgain
Effective gain applied to every sample.
ui/src/audio.rs:47
↓ 1 callersMethodgamepak_cycles
`GamePak` ROM access cycles. A 32-bit access is two 16-bit bus accesses: the first sequential or not depending on the caller, the second always sequen
emu/src/bus.rs:1353
↓ 1 callersMethodgamepak_waits
Non-sequential (N) and sequential (S) wait cycles for a `GamePak` ROM wait-state region, read from `WAITCNT`.
emu/src/bus.rs:1329
↓ 1 callersMethodget_affine_params
(&self, reg: &Registers)
emu/src/cpu/hardware/lcd/layers/layer_3.rs:73
↓ 1 callersFunctionget_attributes
(oam_memory: &[u8])
emu/src/cpu/hardware/lcd/object_attributes.rs:458
↓ 1 callersMethodget_bg0_character_base_block
Get BG0 character base block (0-3). Each block is 16KB starting at VRAM `0x0600_0000`. Block N starts at offset N × 0x4000.
emu/src/cpu/hardware/lcd/registers.rs:209
↓ 1 callersMethodget_bg0_color_mode
Get BG0 color mode. Returns `false` for 4bpp (16 colors per palette), `true` for 8bpp (256 colors).
emu/src/cpu/hardware/lcd/registers.rs:223
↓ 1 callersMethodget_bg0_enabled
(&self)
emu/src/cpu/hardware/lcd/registers.rs:143
↓ 1 callersMethodget_bg0_priority
Get BG0 priority (0-3, lower = higher priority).
emu/src/cpu/hardware/lcd/registers.rs:201
↓ 1 callersMethodget_bg0_screen_base_block
Get BG0 screen base block (0-31). Each block is 2KB (one 32×32 tilemap). Block N starts at VRAM offset N × 0x800.
emu/src/cpu/hardware/lcd/registers.rs:216
↓ 1 callersMethodget_bg0_screen_size
Get BG0 screen size in pixels for text mode backgrounds. Text backgrounds can span multiple screen blocks arranged in a grid: | Size bits | Dimensio
emu/src/cpu/hardware/lcd/registers.rs:239
↓ 1 callersMethodget_bg1_character_base_block
Get BG1 character base block (0-3).
emu/src/cpu/hardware/lcd/registers.rs:255
↓ 1 callersMethodget_bg1_color_mode
Get BG1 color mode (`false` = 4bpp, `true` = 8bpp).
emu/src/cpu/hardware/lcd/registers.rs:265
↓ 1 callersMethodget_bg1_enabled
(&self)
emu/src/cpu/hardware/lcd/registers.rs:147
↓ 1 callersMethodget_bg1_priority
Get BG1 priority (0-3, lower = higher priority).
emu/src/cpu/hardware/lcd/registers.rs:250
↓ 1 callersMethodget_bg1_screen_base_block
Get BG1 screen base block (0-31).
emu/src/cpu/hardware/lcd/registers.rs:260
↓ 1 callersMethodget_bg1_screen_size
Get BG1 screen size in pixels. See [`get_bg0_screen_size`](Self::get_bg0_screen_size).
emu/src/cpu/hardware/lcd/registers.rs:270
↓ 1 callersMethodget_bg2_character_base_block
Get BG2 character base block (0-3).
emu/src/cpu/hardware/lcd/registers.rs:286
↓ 1 callersMethodget_bg2_color_mode
Get BG2 color mode (`false` = 4bpp, `true` = 8bpp).
emu/src/cpu/hardware/lcd/registers.rs:296
↓ 1 callersMethodget_bg2_enabled
(&self)
emu/src/cpu/hardware/lcd/registers.rs:151
↓ 1 callersMethodget_bg2_priority
Get BG2 priority (0-3, lower = higher priority).
emu/src/cpu/hardware/lcd/registers.rs:281
↓ 1 callersMethodget_bg2_screen_base_block
Get BG2 screen base block (0-31).
emu/src/cpu/hardware/lcd/registers.rs:291
↓ 1 callersMethodget_bg2_screen_size
Get BG2 screen size in pixels for text mode. See [`get_bg0_screen_size`](Self::get_bg0_screen_size). Note: In affine modes (1-2), BG2 uses different
emu/src/cpu/hardware/lcd/registers.rs:303
↓ 1 callersMethodget_bg3_character_base_block
Get BG3 character base block (0-3).
emu/src/cpu/hardware/lcd/registers.rs:319
↓ 1 callersMethodget_bg3_color_mode
Get BG3 color mode (`false` = 4bpp, `true` = 8bpp).
emu/src/cpu/hardware/lcd/registers.rs:329
↓ 1 callersMethodget_bg3_enabled
(&self)
emu/src/cpu/hardware/lcd/registers.rs:155
↓ 1 callersMethodget_bg3_priority
Get BG3 priority (0-3, lower = higher priority).
emu/src/cpu/hardware/lcd/registers.rs:314
↓ 1 callersMethodget_bg3_screen_base_block
Get BG3 screen base block (0-31).
emu/src/cpu/hardware/lcd/registers.rs:324
↓ 1 callersMethodget_bg3_screen_size
Get BG3 screen size in pixels for text mode. See [`get_bg0_screen_size`](Self::get_bg0_screen_size).
emu/src/cpu/hardware/lcd/registers.rs:334
↓ 1 callersMethodget_bg_control
(&self, reg: &Registers)
emu/src/cpu/hardware/lcd/layers/layer_3.rs:87
↓ 1 callersMethodget_blend_alpha
Get alpha blending coefficients (EVA, EVB) from BLDALPHA. Both are 0-16, representing 0/16 to 16/16 blend factors.
emu/src/cpu/hardware/lcd/registers.rs:517
↓ 1 callersMethodget_blend_mode
Get the blend mode from BLDCNT. 0 = Off, 1 = Alpha blend, 2 = Brightness increase (white), 3 = Brightness decrease (black)
emu/src/cpu/hardware/lcd/registers.rs:485
↓ 1 callersMethodget_blend_target1
Get first target layers for blending (BLDCNT bits 0-5). Returns (BG0, BG1, BG2, BG3, OBJ, Backdrop) as targets.
emu/src/cpu/hardware/lcd/registers.rs:491
↓ 1 callersMethodget_blend_target2
Get second target layers for alpha blending (BLDCNT bits 8-13). Returns (BG0, BG1, BG2, BG3, OBJ, Backdrop) as targets.
emu/src/cpu/hardware/lcd/registers.rs:504
↓ 1 callersMethodget_char_base_block
(&self, reg: &Registers)
emu/src/cpu/hardware/lcd/layers/layer_0.rs:123
↓ 1 callersMethodget_color_mode
(&self, reg: &Registers)
emu/src/cpu/hardware/lcd/layers/layer_0.rs:127
↓ 1 callersMethodget_hblank_irq_enable
(&self)
emu/src/cpu/hardware/lcd/registers.rs:180
↓ 1 callersMethodget_idx_in_if
(self)
emu/src/bus.rs:121
↓ 1 callersMethodget_obj_enabled
(&self)
emu/src/cpu/hardware/lcd/registers.rs:159
↓ 1 callersMethodget_operand
Gets the second operand for an ALU instruction. # Panics Panics if register index conversion fails.
emu/src/cpu/arm/operations.rs:347
↓ 1 callersMethodget_priority
(&self, reg: &Registers)
emu/src/cpu/hardware/lcd/layers/layer_0.rs:131
↓ 1 callersMethodget_reference_point
(&self, reg: &Registers)
emu/src/cpu/hardware/lcd/layers/layer_3.rs:83
↓ 1 callersMethodget_registers
Get all 16 registers as an array.
ui/src/emu_thread.rs:674
↓ 1 callersMethodget_screen_base_block
(&self, reg: &Registers)
emu/src/cpu/hardware/lcd/layers/layer_0.rs:119
↓ 1 callersMethodget_screen_size
(&self, reg: &Registers)
emu/src/cpu/hardware/lcd/layers/layer_0.rs:115
↓ 1 callersMethodget_scroll
(&self, reg: &Registers)
emu/src/cpu/hardware/lcd/layers/layer_0.rs:111
↓ 1 callersMethodget_vblank_irq_enable
(&self)
emu/src/cpu/hardware/lcd/registers.rs:176
↓ 1 callersMethodget_vcount_setting
(&self)
emu/src/cpu/hardware/lcd/registers.rs:172
↓ 1 callersMethodget_vcounter_irq_enable
(&self)
emu/src/cpu/hardware/lcd/registers.rs:184
↓ 1 callersMethodget_win0_bottom
(&self)
emu/src/cpu/hardware/lcd/registers.rs:380
↓ 1 callersMethodget_win0_enabled
Check if Window 0 is enabled (DISPCNT bit 13).
emu/src/cpu/hardware/lcd/registers.rs:356
↓ 1 callersMethodget_win0_enables
Get layer enable flags for pixels inside Window 0. Returns tuple of (BG0, BG1, BG2, BG3, OBJ, color effects) enable flags. When a flag is false, that
emu/src/cpu/hardware/lcd/registers.rs:402
↓ 1 callersMethodget_win0_left
Window 0 boundary coordinates (from WIN0H and WIN0V registers)
emu/src/cpu/hardware/lcd/registers.rs:371
↓ 1 callersMethodget_win0_right
(&self)
emu/src/cpu/hardware/lcd/registers.rs:374
↓ 1 callersMethodget_win0_top
(&self)
emu/src/cpu/hardware/lcd/registers.rs:377
↓ 1 callersMethodget_win1_bottom
(&self)
emu/src/cpu/hardware/lcd/registers.rs:394
↓ 1 callersMethodget_win1_enabled
Check if Window 1 is enabled (DISPCNT bit 14).
emu/src/cpu/hardware/lcd/registers.rs:361
↓ 1 callersMethodget_win1_enables
Get layer enable flags for pixels inside Window 1. Returns tuple of (BG0, BG1, BG2, BG3, OBJ, color effects) enable flags.
emu/src/cpu/hardware/lcd/registers.rs:416
↓ 1 callersMethodget_win1_left
Window 1 boundary coordinates (from WIN1H and WIN1V registers)
emu/src/cpu/hardware/lcd/registers.rs:385
↓ 1 callersMethodget_win1_right
(&self)
emu/src/cpu/hardware/lcd/registers.rs:388
↓ 1 callersMethodget_win1_top
(&self)
emu/src/cpu/hardware/lcd/registers.rs:391
↓ 1 callersMethodget_window_layer_enables
Determine which layers are enabled at this pixel based on window settings. Returns (bg0, bg1, bg2, bg3, obj, effects) enable flags.
emu/src/cpu/hardware/lcd.rs:498
↓ 1 callersMethodget_winobj_enabled
Check if Object Window is enabled (DISPCNT bit 15).
emu/src/cpu/hardware/lcd/registers.rs:366
↓ 1 callersMethodget_winobj_enables
Get layer enable flags for pixels inside Object Window. Returns tuple of (BG0, BG1, BG2, BG3, OBJ, color effects) enable flags. WINOBJ applies to pix
emu/src/cpu/hardware/lcd/registers.rs:446
↓ 1 callersMethodget_winout_enables
Get layer enable flags for pixels outside all windows. Returns tuple of (BG0, BG1, BG2, BG3, OBJ, color effects) enable flags. These settings apply w
emu/src/cpu/hardware/lcd/registers.rs:431
↓ 1 callersMethodhalf_word_data_transfer
( &mut self, indexing: Indexing, offsetting: Offsetting, write_back: bool,
emu/src/cpu/arm/operations.rs:691
↓ 1 callersMethodhandle_enter_vdraw
(&mut self, memory: &Memory, registers: &Registers)
emu/src/cpu/hardware/lcd/layers/layer_obj.rs:668
↓ 1 callersMethodhandle_input
Handle keyboard input and send button commands to the emulator.
ui/src/app.rs:278
↓ 1 callersMethodhandle_swi_hle
Handle SWI calls with High-Level Emulation Returns true if handled, false if BIOS should handle it
emu/src/cpu/arm7tdmi.rs:1069
↓ 1 callersMethodheal_pokemon
Quick cheat: Max out current HP.
ui/src/pokemon_debugger.rs:935
↓ 1 callersMethodhi_reg_operation_branch_ex
( &mut self, op: ThumbHighRegisterOperation, reg_source: u16, reg_destination:
emu/src/cpu/thumb/operations.rs:209
↓ 1 callersMethodinit_audio
Wire up audio output. Creates a lock-free sample ring feeding the host audio device at `output_rate` Hz and returns the consumer end. The emulator pus
emu/src/gba.rs:118
↓ 1 callersMethodinitialize_stack_pointers
Initialize stack pointers for all CPU modes to match GBA BIOS behavior
emu/src/cpu/arm7tdmi.rs:860
↓ 1 callersMethodis_bit_off
(&self, bit_idx: u8)
emu/src/bitwise.rs:24
↓ 1 callersMethodis_in_win0
Check if a screen coordinate is inside Window 0's bounds. Window coordinates handle wrap-around: if right < left, the window extends from left edge t
emu/src/cpu/hardware/lcd/registers.rs:462
↓ 1 callersMethodis_in_win1
Check if a screen coordinate is inside Window 1's bounds. See [`is_in_win0`](Self::is_in_win0) for wrap-around behavior.
emu/src/cpu/hardware/lcd/registers.rs:474
↓ 1 callersMethodis_in_winobj
Check if a pixel is covered by the Object Window.
emu/src/cpu/hardware/lcd/layers/layer_obj.rs:664
↓ 1 callersMethodlatch
Latch the source, destination and count into the internal registers, done when the channel is enabled.
emu/src/cpu/hardware/dma.rs:42
↓ 1 callersMethodlevel_up
Quick cheat: Increment level by 1. This properly modifies the encrypted experience value and recalculates the checksum.
ui/src/pokemon_debugger.rs:1074
↓ 1 callersMethodload_address
(&mut self, sp: bool, r_destination: usize, offset: u32)
emu/src/cpu/thumb/operations.rs:476
↓ 1 callersMethodload_state
(&mut self)
ui/src/savegame.rs:85
↓ 1 callersMethodload_store_halfword
Executes a halfword load/store instruction. # Panics Panics if address conversion fails.
emu/src/cpu/thumb/operations.rs:413
↓ 1 callersMethodload_store_immediate_offset
Executes a load/store with immediate offset. # Panics Panics if address conversion fails.
emu/src/cpu/thumb/operations.rs:369
↓ 1 callersMethodload_store_register_offset
Executes a load/store with register offset. # Panics Panics if address conversion fails.
emu/src/cpu/thumb/operations.rs:278
↓ 1 callersMethodload_store_sign_extend_byte_halfword
Executes a load/store with sign extension for byte/halfword. # Panics Panics if register index or address conversion fails.
emu/src/cpu/thumb/operations.rs:320
↓ 1 callersMethodlong_branch_link
(&mut self, h: bool, offset: u32)
emu/src/cpu/thumb/operations.rs:651
↓ 1 callersMethodmix_dma_sound
(&self)
emu/src/cpu/hardware/sound.rs:640
↓ 1 callersMethodmix_psg
(&self)
emu/src/cpu/hardware/sound.rs:667
↓ 1 callersMethodmove_compare_add_sub_imm
(&mut self, op: Operation, r_destination: u16, offset: u32)
emu/src/cpu/thumb/operations.rs:59
↓ 1 callersMethodmove_shifted_reg
(&mut self, op: ShiftKind, offset5: u16, rs: u16, rd: u16)
emu/src/cpu/thumb/operations.rs:20
↓ 1 callersMethodmul
(self, rhs: RotationScaling)
emu/src/cpu/hardware/lcd/point.rs:53
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