Method compile

expander_compiler/src/layering/compile.rs:102–145

(&mut self)

impl<'a, C: Config, I: InputType> CompileContext<'a, C, I> {
    pub fn compile(&mut self) {
        // 1. do a toposort of the circuits
        self.dfs_topo_sort(0);

        // 2. compute min and max layers for each circuit
        for id in self.order.clone() {
            self.compute_min_max_layers(id);
        }

        // 3. prepare layer layout contexts
        for id in self.order.clone() {
            self.prepare_layer_layout_context(id);
        }

        // 4. solve layer layout for root circuit (it also recursively solves all required sub-circuits)
        let mut layout_ids = Vec::with_capacity(self.circuits[&0].output_layer + 1);
        for i in 0..=self.circuits[&0].output_layer {
            layout_ids.push(self.solve_layer_layout(&LayerReq {
                circuit_id: 0,
                layer: i,
            }));
        }
        self.layout_ids = layout_ids;
        if !self.opts.allow_input_reorder {
            let layout_vec =
                merge_layouts(vec![], (0..self.circuits[&0].lcs[0].vars.len()).collect());
            let id = self.layer_layout_pool.add(&LayerLayout {
                circuit_id: 0,
                layer: 0,
                size: layout_vec.len(),
                inner: super::layer_layout::LayerLayoutInner::Dense {
                    placement: layout_vec,
                },
            });
            self.layout_ids[0] = id;
        }

        // 5. generate wires
        let layers = self.connect_wires(&self.layout_ids.clone());
        self.layers = layers;

        // 6. record the input order (used to generate witness)
        self.input_order = self.record_input_order();
    }

    fn dfs_topo_sort(&mut self, id: usize) {
        if self.circuits.contains_key(&id) {